This is a basic course on Computer Organization and Architecture . This course is meant for Engineering Students of Electrical, Electronics & Communication, Computer Science and This course is not only beneficial for students to earn credits as a part of their course curriculum but also score well in competitive exams. The Complete Course is divided into Five Sections. Section-1 Covers Differences between Computer Organization and Architecture, Functional Blocks of Computer, Register Organization of Section-2 covers Data Representation of Signed numbers, Fixed and Floating Point Numbers and Characters, Computer Arithmetic, Ripple Carry Adder, Carry Look Ahead Adder, Multiplication by Shift & Add, Booth’s Algorithm, Multiplication by Carry Save addition, Restoring Division Algorithm, Non Restoring Division Algorithm. Section-3 Covers Peripheral Devices and their characteristics: Input-Output Subsystems, I/O Device Interface, I/O transfers – Program Controlled, Interrupt Driven and DMA, Privileged and Non-Privileged Instructions, Software Interrupts and Exceptions, Programs and Processes – Role of Interrupts in Process State Transitions, I/O Device Interfaces –Section-4 Covers Basic concepts of Pipelining, Throughput and Speedup, Pipeline Hazards, Introduction to Parallel Processors, Concurrent access to Memory and Cache Coherency. Section-5 covers Memory Organization, Memory Interleaving, Concept of Hierarchical Memory Organization, Cache Memory, Cache Size vs. Block Size, Mapping Functions, Replacement Algorithms, Write Policies.
Students will be able to understand difference between computer Organization & Architecture, Functional blocks of Computer and Register Organization of CPU.
Students will learn CPU Organization : General Register Organization, Single Accumulator Organization and Stack organization with Zero, one, two and three address instructions.
Students will be able to learn various addressing modes of microprocessor : Implied, direct, Indirect, Immediate, Register, Register Indirect, Auto Increment, Auto Decrement, Indexed, Base Register addressing modes with example.
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