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Verification Series Part 4

Hands-On UVM Projects

Kumar Khandagle

Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.

Read more

Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.

This is a Lab-based course designed such that anyone with the fundamentals of UVM could understand how verification engineers use UVM to perform verification of commonly used RTLs and sub-blocks in FPGA.  The course covers verification of the combinational circuit like combinational adder, Sequential circuit like Data flip-flop, communication interfaces like a clock generator

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What's inside

Learning objectives

  • Verification of combinational circuits
  • Verification of sequential circuits
  • Verification of common bus protocols viz. apb, axi
  • Verification of communication protocols viz. uart, spi, i2c
  • Understanding usage of virtual sequencer, sequence library and tlm analysis fifo

Syllabus

Agenda
Course Overview
Course Pre-requisites
Verification of Combinational Circuit : 4-bit Multiplier
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Multiplier P1
Multiplier P2
Multiplier P3
Design Code
Verification Environment
Verification of Sequential Circuit : Data Flipflop
DFF P1
DFF P3
Verification Code
Understanding SPI Memory
Verification of UART
Clock Generator for different Baud
Verification P1
Verification P2
Clock Generator : Design
Clock Generator : Verification environment
Understanding UART system
UART Clock Generator
UART Transmitter
UART Receiver
System Top
Typical Transaction
Simple TB code
Verification Environment P1
Verification Environment P2
Verification of SPI Memory
Understanding SPI Controller RTL
Typical Transactions
SPI controller P1
SPI controller P2
Understanding Native Transactions
Native SPI P1
Native SPI P2
Design Code : Native
Verification Environment : Native
Verification of I2C Memory
Understanding I2C
I2C Slave Memory
I2C Master Controller
Typical Transaction to DUT
Veriicantion of APB_RAM
Fundamentals
Understanding Design
Understanding Transactions
ABP_RAM P1
ABP_RAM P2
ABP_RAM P3
Verification Environment
Verification of AXI Memory
Understanding AXI Channels
Write address Channel
Write Data Channel
Write Response Channel
Single Write Transaction
Implementing Write Channel P1
Understanding Burst Type P1
Understanding Burst Type P2
Understanding Burst Type P3
Implementing Write Data Channel
Implementing Write Response Channel
Read Channel
Implementing Read Channel
Verification Environment P3
Understanding usage of Sequence Library
Sequence Library P1
Sequence Library P2
Code
Understanding TLM Analysis FIFO
Understanding TLM FIFO usage
Demonstration
Usage of TLM Analysis FIFO P1 : Design
Usage of TLM Analysis FIFO P1 : Verification Env P1
Usage of TLM Analysis FIFO P1 : Verification Env P2
Usage of TLM Analysis FIFO P1 : Verification Env P3
Understanding Virtual Sequencer
Virtual Sequencer P1
Virtual Sequencer P2
DUT

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Activities

Be better prepared before your course. Deepen your understanding during and after it. Supplement your coursework and achieve mastery of the topics covered in Verification Series Part 4: Hands-On UVM Projects with these activities:
Review SystemVerilog Fundamentals
Reinforce your understanding of SystemVerilog syntax and semantics, which are essential for writing UVM testbenches.
Show steps
  • Review SystemVerilog syntax and data types.
  • Practice writing simple SystemVerilog modules.
  • Study SystemVerilog constructs for testbenches.
Read 'A Practical Guide to SystemVerilog'
Gain a deeper understanding of SystemVerilog concepts and their application in UVM-based verification.
View SystemVerilog for Verification on Amazon
Show steps
  • Read the chapters on SystemVerilog data types and constructs.
  • Study the examples of SystemVerilog testbenches.
  • Take notes on key concepts and syntax.
Implement a UVM Testbench for a Simple FIFO
Apply your UVM knowledge by building a complete testbench for a common hardware component.
Show steps
  • Define the FIFO interface and functionality.
  • Create UVM components: driver, monitor, agent, and environment.
  • Implement sequences to generate stimulus and check responses.
  • Run simulations and debug the testbench.
Four other activities
Expand to see all activities and additional details
Show all seven activities
Write UVM Sequences for Different Stimulus Patterns
Improve your ability to generate complex stimulus scenarios using UVM sequences.
Show steps
  • Define different stimulus patterns (e.g., burst writes, random reads).
  • Implement UVM sequences to generate these patterns.
  • Verify the sequences by observing the DUT behavior.
Document Your UVM Testbench Architecture
Solidify your understanding of UVM architecture by creating a detailed documentation of your testbench.
Show steps
  • Create a block diagram of the UVM testbench.
  • Describe the functionality of each UVM component.
  • Explain the data flow and interactions between components.
  • Include code snippets and examples.
Explore 'Verification Methodology Manual for SystemVerilog'
Deepen your understanding of UVM principles and best practices for advanced verification.
View Putting Knowledge to Work on Amazon
Show steps
  • Read the chapters on UVM architecture and components.
  • Study the examples of UVM testbenches for complex designs.
  • Take notes on key concepts and design patterns.
Contribute to an Open-Source UVM Project
Gain practical experience by contributing to a real-world UVM project and collaborating with other engineers.
Show steps
  • Find an open-source UVM project on GitHub or similar platform.
  • Identify a bug or feature to work on.
  • Implement the fix or feature and submit a pull request.
  • Respond to feedback and iterate on your contribution.

Career center

Learners who complete Verification Series Part 4: Hands-On UVM Projects will develop knowledge and skills that may be useful to these careers:
Verification Engineer
Becoming a Verification Engineer often involves ensuring the quality and correctness of hardware designs through rigorous testing and validation. This course directly aligns with the responsibilities of a verification engineer, since it emphasizes hands-on UVM projects for verifying RTL designs used in FPGAs. By covering verification of combinational and sequential circuits, along with common communication interfaces and bus protocols, the course directly prepares you to tackle real-world verification challenges. The focus on UVM and its application to various hardware components would be valuable to someone in this role.
See salaries and explore the career path for Verification Engineer
System on Chip Verification Engineer
System on Chip Verification Engineers specialize in SoC verification, requiring a deep understanding of complex system architectures, verification methodologies, and industry standard tools. This course would be very useful because it emphasizes hands-on UVM projects, which have become a de facto standard for RTL design verification. By covering the essentials of UVM and its application to verifying RTL designs, the course directly addresses the skills this kind of engineer needs. Additionally, the coverage of communication interfaces and bus protocols may give the aspiring System on Chip Verification Engineer the knowledge they need to excel.
See salaries and explore the career path for System on Chip Verification Engineer
RTL Verification Engineer
An RTL Verification Engineer ensures the correctness and reliability of Register Transfer Level designs, which are used to model digital circuits. This course is designed such that anyone with UVM fundamentals can verify the usage of UVM to perform verification of commonly used RTLs. Additionally, this course covers sequential circuits like data flip-flops and communication interfaces like clock generators. This aligns with the demands of RTL verification. By understanding the course material, one may improve their skill to verify RTL designs, which may be valuable to an RTL Verification Engineer.
See salaries and explore the career path for RTL Verification Engineer
ASIC Verification Engineer
An ASIC Verification Engineer is responsible for verifying the functionality and performance of Application Specific Integrated Circuits. This course provides insights into the verification methodologies and practices essential for success. Course coverage of UVM, test benches, System Verilog, combinational circuit verification, sequential circuit verification, and communication protocol verification addresses the fundamental skills required for ASIC verification. By studying this course, the potential ASIC Verification Engineer would gain practical experience with the UVM framework, and proficiency in writing effective test benches.
See salaries and explore the career path for ASIC Verification Engineer
Digital Design Verification Engineer
Digital Design Verification Engineers focus on verifying digital circuits and systems, ensuring they meet specifications and function correctly, which heavily relies on the knowledge of hardware verification languages and methodologies. This course may aid in the process of becoming a Digital Design Verification Engineer since it focuses on UVM which promotes reusability, and helps verification engineers quickly locate hidden bugs. You may improve your understanding of bug detection following this course. Furthermore, the addition of the configuration database shifts the way users work with verification languages, a skill taught by the course.
See salaries and explore the career path for Digital Design Verification Engineer
Verification IP Developer
The role of a Verification IP Developer involves creating reusable verification components and environments, often requiring expertise in SystemVerilog and UVM. This course's hands-on UVM projects, designed to help understand how verification engineers use UVM to perform verification of commonly used RTLs and sub-blocks in FPGAs, aligns with the need to build reusable VIP. The course emphasis on bus protocols, such as APB and AXI, as well as the use of TLM analysis FIFOs, may aid in verification. If you wish to pursue a career in Verification IP development, a strong foundation in UVM is essential.
See salaries and explore the career path for Verification IP Developer
FPGA Engineer
An FPGA Engineer develops and implements digital systems using Field Programmable Gate Arrays. This course may enhance the capabilities needed for this role, especially since the course description explicitly mentions verifying RTL and sub-blocks in FPGAs. The course's focus on UVM projects, combinational circuits, sequential circuits, and communication protocols directly aligns with the tasks involved in FPGA development and verification. The hands-on approach and coverage of industry-standard verification methodologies should be especially helpful for aspiring FPGA Engineers.
See salaries and explore the career path for FPGA Engineer
Hardware Design Engineer
The role of the Hardware Design Engineer is to develop and implement digital circuits and systems. This course may enhance your capabilities in this area, especially concerning the verification aspect of hardware development. The course covers writing test benches and using System Verilog to locate bugs, which is a crucial part of ensuring a design is bug-free. Furthermore, the UVM framework, as covered in the course, provides a structured approach that can refine methodology. The practical exercises on combinational and sequential circuits, such as multipliers and flip-flops, may be useful for hardware design.
See salaries and explore the career path for Hardware Design Engineer
Hardware Verification Consultant
Hardware Verification Consultants provide expert advice and services to companies needing to verify complex hardware designs, so expertise with hardware verification languages and methodologies is critical for this role. The emphasis of this course is hands-on UVM projects, which have quickly become a de facto standard. This is a useful skill for consultants. The course's lab-based approach provides a good way to understand how engineers use UVM to perform verification of commonly used RTLs and sub-blocks. This may improve understanding of UVM.
See salaries and explore the career path for Hardware Verification Consultant
Principal Verification Engineer
A Principal Verification Engineer typically leads verification efforts on complex projects, so experience with planning, execution, and debugging is necessary. While this role often requires seniority, this course may be helpful in keeping up with the latest developments in verification technology. This course's emphasis is on hands-on UVM projects, which have quickly become a de facto standard. Participants may strengthen their understanding of topics such as virtual sequencers, sequence libraries, and TLM (Transaction Level Modeling) analysis FIFOs. This course is lab-based.
See salaries and explore the career path for Principal Verification Engineer
Design Verification Manager
A Design Verification Manager typically oversees a team of verification engineers, managing project timelines, resources, and technical direction. These roles often require seniority, but this course may sharpen understanding of some of the fundamentals. It gives experience with hands-on UVM projects, which have quickly become a de facto standard in the field. Participants may strengthen their understanding of topics such as virtual sequencers, sequence libraries, and TLM analysis FIFOs. This course is lab-based, providing a practical skill-set.
See salaries and explore the career path for Design Verification Manager
Hardware Engineer
Hardware Engineers design, develop, and test computer systems and components. This course may augment the capabilities needed for this role, especially since the course description explicitly mentions various integrated circuit components. The course's focus on UVM projects, combinational circuits, sequential circuits, and communication protocols may assist in the development of integrated circuits. The hands-on approach and coverage of industry-standard verification methodologies may be useful for hardware design.
See salaries and explore the career path for Hardware Engineer
Electronics Engineer
Electronics Engineers research, design, develop, and test electronic components and systems. This course may enhance the skillset required for designing and testing digital components. The course's focus on UVM, combinational circuits, sequential circuits, and communication protocols may enhance the candidate's understanding of digital verification. The course may be particularly useful for Electronics Engineers whose work touches verification.
See salaries and explore the career path for Electronics Engineer
Computer Engineer
Computer Engineers research, design, develop, and test computer systems and components, which relies on a strong understanding of both hardware and software. This course may enhance the capabilities needed for this role, especially as it concerns hardware verification. The course's focus on UVM projects, combinational circuits, sequential circuits, and communication protocols, may enhance the ability to test components and systems. The hands-on approach and coverage of industry-standard verification methodologies would be helpful to Computer Engineers.
See salaries and explore the career path for Computer Engineer
CAD Engineer
Computer Aided Design Engineers develop and maintain software tools used in the design and verification of integrated circuits. While this course may not be directly related to software development, it may improve knowledge of the verification process, helping CAD Engineers understand the needs of verification teams. By learning about UVM, test benches, and System Verilog, the Computer Aided Design Engineer may gain insights that aid in tool development and support.
See salaries and explore the career path for CAD Engineer

Reading list

We've selected two books that we think will supplement your learning. Use these to develop background knowledge, enrich your coursework, and gain a deeper understanding of the topics covered in Verification Series Part 4: Hands-On UVM Projects.
Cover image
SystemVerilog for Verification
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Provides a comprehensive overview of SystemVerilog, covering both language fundamentals and advanced verification techniques. It is particularly useful for understanding the practical aspects of SystemVerilog and how it is used in real-world verification projects. The book serves as a valuable reference throughout the course and beyond, offering detailed explanations and practical examples. It is commonly used as a textbook in university courses on digital design verification.
SystemVerilog for Verification
Paperback
Check
SystemVerilog for Verification
Kindle Edition
Check
Cover image
Putting Knowledge to Work
Save
Provides a comprehensive guide to the Universal Verification Methodology (UVM) and its application in complex verification projects. It covers the key concepts and principles of UVM, as well as practical examples and guidelines for implementing UVM-based testbenches. While it may be more valuable as additional reading, it offers a deeper understanding of the UVM framework and its benefits. This book is commonly used by industry professionals and advanced students.
Putting Knowledge to Work
Paperback
Check
Putting Knowledge to Work
Kindle Edition
Check

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8.5 total hours
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Instructor
Kumar Khandagle
Language
English
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