Learn VHDL, ISE and FPGA by Designing a basic Home Alarm

You will be introduced to the device called Field Programmable Gate Array and how is it used in the industry. You will understand, in basic terms, the differences between ASSP, FPGA and ASIC.

LUTs stands for Look Up Tables and they are crucial part of the FPGA's, along with the Flip Flops. This Lecture takes a look at how any digital system can be seen as interconnected LUTs and Flip Flops and the flexibility of FPGA's come from programmable interconnects. FPGA's generally come with volatile memory and so it must either be programmed every time it is powered up using a cable or alternatively, the programming bit stream can be stored in a Read Only Memory on the board, which will program the FPGA at power up instead of using a cable.

This is the first opportunity in the course to look at the resources available on a Xilinx device using the Xilinx tool called FPGA Editor. This demo will be about opening an example design, navigate around and see how blocks are connected.

Note: You are not expected to try it at this stage presuming that you do not have ISE installed on your machine. If you have already installed ISE, you may go ahead and try this demo but if not, you can wait for Lecture 7 and 8, which explain how to download ISE, install it and get a license for it. Lecture 9 and 10 explain about the Project Navigator and How to open FPGA Editor, respectively.

It is important to understand the flow in ISE to effectively use the tools and debug issues that you may encounter. The user would describe the hardware he/she is trying to implement, in terms of a language called HDL, for Hardware Description Language. Section 4 is devoted to one of the HDL's, called VHDL. The coded description of the hardware is then Synthesized by Xilinx Synthesis Tool (XST). This produces a netlist in terms of interconnected components that exist on the device. So compilation state stage takes in HDL codes and output a netlist. Under the hood, each device has a library of components that the compiler maps to in order to produce a netlist.

After synthesis, the netlist will go through implementation and a different netlist will be produced at each stage. Implementation consists of three major stages: Translate, MAP and Place & Route. Implementation is done to fit the netlist on actual locations on the device.

Translate will take the synthesized netlist and add constraints to it. Then MAP will do the placement and optimization of the netlist to fit the device. Place & Route will do more placement and will route the nets.

Note that we are still in the domain of software processing of the design and it is only after implementation that the bitstream will be generated. This bitstream can then be used to physically program the FPGA.

This Lecture gives the steps that you will have to undertake to Download and Install the ISE Webpack, which is a free version of ISE that allows one to use all the features of the tool for certain small devices.

Following Download and Installation of the tool, a Webpack license will be needed to be able to open ISE. It is advised to generate a node-locked license to your machine. This Lecture explains how a .lic file can be read by the Xilinx License Manager tool to show the features available for that license.

The Project Navigator is a GUI that allows the user to access the whole range of programs in one GUI. A user will be able to create a project, run Synthesis, run Implementation and many other programs from there. This lecture is a demo of how an example design is opened in Project Navigator, with explanation on the different features of the GUI.

Now that you understand how ISE tools are accessed, this lecture explains how to open FPGA Editor. If you haven't tried the demo of Lecture 5, you will be able to try it after this present Lecture.

The VHDL file is generally structured into

1. Entity part : this describes the outer part of the VHDL file, namely the ports
2. Architecture part: this describes the inner part of the VHDL file, and
3. in most designs, there are processes and processes are written inside the architecture part

Processes come as synchronous or asynchronous processes. Synchronous processes updated with clock edges, while asynchronous processes are updated with respected to non clock signals.

Processes work almost independently to each other and they should be seen as working in parallel.

This is the starting point of understanding VHDL.The rest of the what you will learn will go in the architecture part.

As in other programming languages, VHDL also has different data types. Since we are dealing with hardware and digital electronics, the data will be ultimately in bits form i.e 1's and 0's but in VHDL file, the data can be in non binary forms such as integers. There is also signed and unsigned data, which are commonly used in VHDL.

This Lecture gives an overview of the Operators that are available in VHDL. Operators are Logical, e.g AND, OR, XOR, or Arithmetic, e.g Addition, Subtraction.

This is the first piece of code that you will create and it is simple linking between two ports (one input to one output port).

ISE comes with Technology Viewer and RTL Schematic Viewer to help the designer understand the logic that is synthesized. These are visual representation of the synthesized netlists. For example, if a designer describes a Shift Register in VHDL and would like to confirm whether a Shift Register was actually *inferred, he/she would either check the Synthesis report or use the RTL/Technology Schematic Viewer.

Note: inference is the term used to describe what the compiler does when it creates a component in the netlist based on the HDL coding or in other words it is the compiler 'understanding' the codes in terms of the technology.

You will take another step into VHDL coding by creating a NOT gate and it is done very easily.

In this Lecture, we are going to describe an AND gate and secondly, an OR gate in the design.

Some more examples of gates will be described: XOR and NOR gates

Up till now, we have been dealing with Standard Logic data as input and output. Now we are going to extend Standard Logic into the bus or vector version of the data type. It is called Std_logic_vector.

More output and gates will be added to produce a 'Logic Unit' i.e a unit that performs many logical operation on two std_logic inputs.

All the previous operations were asynchronous and now we will create a synchronous process. A clock input will be added and a synchronous process will be written which will contain a simple inverter code.

The Technology Schematic from the previous Lecture will not be as expected and the reason for this will be explained. This Lecture will show how a synthesis option can be changed to have the expected schematics, although both schematics are equivalent in terms of behavior and not in terms of resources. This is just a demo of the effect of a single synthesis option but there are many more of these options that have different effects.

Based on the experience you gained with synchronous processes, we are now going to transform the Logic Unit designed previously into a synchronous process by adding a clock and editing the process. The behavioral effect will be that the results will now be updated only at the active clock edges - previously the output would update almost instantly based on the input.

In a general digital system, there are many advantages to design in synchronous and FPGA's are specially built to run synchronous designs. So almost all FPGA designs are expected to be synchronous to prevent complications. An asynchronous design will be sensitive to delays, which are present on every path and through every component of the FPGA. The problem gets more complicated with temperature and voltage variations, which affects the delay values. A Synchronous design is neater in terms of control over delays by working in stages of registers. For example, if two signals reach an Adder, one of the signal may arrive faster than the other and this will cause the Adder to output a wrong (invalid) result temporarily, while 'waiting' for the slower signal to reach the adder. A synchronous design would have two registers to hold the values and output them at the same time at the clock edge or a register at the output of the Adder will only output valid data when both signals are valid.

The Language Template is a great feature of ISE to help build your codes rapidly. If you need to add a Shift Register in the design, it is easier to go to Language Template, copy and paste the codes into your own code, connect the signals and edit some parameters (e.g shift register length) if needed. This Lecture shows how to synthesize a Flip Flop by using Language Template. Further, it can help the learner to understand how to write VHDL codes.

Language Template also contain synthesizable examples that can be copied verbatim into a blank file to get it synthesized.

This is an example of how to use the Language Template to synthesize a Block RAM example code.

Signals are generally internal to the design and are declared before the 'begin' keyword in architecture. Signals can be use to hold a temporary result in the design.

Constants can be used to set a fixed value in the design.

The syntax for variable is also shown here and an example of use of variable will be shown when functions are explained.

This Lecture explains how arrays are written and initialized. An example of array in the Block RAM codes is used to demonstrate how an array can be useful in a design. The Block RAM codes also shows how they can read values in and out.

Furthermore, multidimensional arrays can be built from the basic principles given here.

Generics are useful syntaxes in VHDL to allow the designer to change the whole structure of the design using the generics value. For example, a Block RAM with flexible size address and data width can be built and code in such a way that the designer only need to edit some generics to change the size of the RAM. The same codes or file can be used or referenced from another file but using different generics values, yielding different sizes of RAM. Hence the codes would be reused.

The addition and subtraction operators are used to infer Adders and Subtractors, respectively. The definition of the symbols '+' and '-' are found in certain libraries and so these libraries should be included when synthesizing these operators.

The same design will be used to add a multiplier using the multiplication operator. After adding these arithmetic operators (+- *) the unit will become an Arithmetic Logic Unit (ALU) used traditionally in processors.

This Lecture talks about Libraries that are in-built in the installation and also of custom libraries that the designer can create to add his/her own files. These files can be used at different places in the project. The custom libraries contain packages.

Package contain declarations, such as signal declarations and constant declarations, and also subprograms such as functions and procedures. For example, a function can be declared in a package and defined there, then somewhere else in another file, the function is used. So instead of writing the function many times, it can be reused in any file in the project by appropriate referencing to the library/package in that file.

The demo includes to create a custom library, a custom package and add a constant in the package.

The 'if' statement is a commonly used conditional statement that allows decisions to be made.

The demo shows how to design a little VHDL file to check where two signals are equal or which one is greater than the other.

The Case statement is useful conditional statement to choose between a number of sets of statements based on the value of a signal. The demo here is that of creating a multiplexer using the Case statement.

Convert the design into a 8-input Mux, 3-bit select

Loops can be useful for repetitive statements. Loops can reduce the number of lines of codes. The demo shown in this Lecture is about reading the Language Template codes for a Shift Register inference. The templates codes contains a For loop and as part of the demo, we are going to 'unroll' the For loop to show the equivalent lines if the For loop was not used.

The Function is used to perform some computations and return one value. The Function should be declared and described, then it can be called by passing some input arguments. The demo for Function involves sending the multiplication operation in the ALU design to a function and the latter is added in the package that was created previously.

This part is about starting a design from scratch and build it step-by-step, until it is programmed on a Basys 2 board.

This lecture gives an overview of how the Home Alarm System will work. The Alarm System will consist mainly of a Finite State Machine to keep track of the state in which it is.

The inputs will be Keypad input, which in this case will be a four-bit data from push buttons on the board. There will also be a Sensors input that will connect to doors and windows in the house but as test on the board, switches will be used to simulate it. As output, there will be a series of LEDs to indicate the state and whether codes are being keyed in. There will also be an Alarm output to link to a loudspeaker but in this case, we will use an LED as alarm indicator.

Finite States Machines are important part of digital design as many designs can be implemented more effectively using state machines. This Lecture shows how the State Diagram of the FSM is drawn for the Alarm System. This will clarify how the system is supposed to work.

This Lecture is about starting the design from scratch and copy the template for an FSM into the blank design.

The states names will now be entered by editing the template codes.

The synchronous process will be edited as per our design. This process is the only process that is synchronous in the FSM codes and it handles the reset and the states updating.

The output process will be edited as per our design. This process determines the output signal values based on the states the machine is in. In other words, the process decodes the output.

The Next State Process will be edited as per our design. This process decodes the next state based on the state the machine is in and the input.

A process will be added to handle the Alarm output and Sensor input. This process will work in parallel with other processes and this will be synchronous to the clock. Note that there can be a number of other ways that these signals can be connected to the FSM and this is only one of them.

Using Push buttons on a board adds a problem that needs to be resolved. The problem is that when a push button is pressed, the sampling of the push button voltage level is done over more than one cycle. For example, instead of a '1' in one cycle, the '1' will be input over several cycles equal to the length of time the push button is pressed. To solve the problem, a debouncer circuit is added and this will create a single pulse of length 1 cycle each time the push button is pressed. This debouncer circuit is also obtained in the Language Template.

This Lecture introduces the concept of Simulation for a VHDL module.

The VHDL module is taken as the Unit Under Test and is considered as a blackbox. A test bench is created to send data into the Unit Under Test and to read from it. The Simulator will use the test bench and UUT to compute the waveforms with respect to time.

The Simulator that will be used is the ISIM, which is a free Simulator that comes with the ISE installation and this Simulator has access to pre-compiled libraries in the installation, hence one doesn't has to compile the libraries before use. It is easy to use for beginners.

ISE also supports third-party Simulators such a ModelSim but to use these Simulators, the libraries need to be compiled.

A test bench is generated automatically by ISE with template lines of codes to help the designer. The main part of the generated test bench that needs editing is the Clock process and Stimulation process. The test bench has the concept of time in it and so it will contain keywords such as 'wait for 10 ns', while this is not normally used in VHDL codes for Synthesis.

Once the test bench is created, the Simulation can be launched and this will result in the opening of a Waveform.

Note that there are different points in the ISE flow at which the Simulation can be run from and the same test bench can be used to do so. In this example, we will launch the Behavioural Simulation and this is the simulation of the VHDL codes before even synthesizing the codes.

The design can also be simulated after synthesis, called post-synthesis simulation. Post-Translate, Post-MAP and Post-PAR Simulation (or Post-Route Simulation) are also possible.

Simulation is simpler and quicker to run at the start of the flow i.e behavioural or post-synthesis but they are less precise in terms of how realistic the results are. Simulation after Place & Route include realistic delays that are close to what will be seen on the hardware.

Real-life designs usually consists of hierarchical designs. So a project might comprise of multiple levels of modules, starting from a top module down. There could be several reasons to design in this way and this include the advantage of integration and reuse of modules previously designed.

This Lecture is explain how a module can be 'instantiated' into another module. The design that has been built so far will be instantiated into a new module called 'Top'. Once this is done, the Top module will contain our design (the one which contains the FSM) as a submodule.

ISE installation comes with pre-designed netlists that designers can readily customize and use in their design. These are called Intellectual Property Cores or IP Cores and each one has a wizard to help the designer with configuring the core.

In this demo, we will add a Digital Clock Manager to show an IP core is customized, generated and instantiated into a VHDL module.

Using a separate tool called PlanAhead, the designer can add location constraints to the design so that they can work on the board. Each pin on the FPGA is fixed on the board and to access the pin, location constraints are added to the ports of the design.

This Lecture explains how location constraints are added for the design on run on a Basys 2 board.

After adding the location constraints, we will add the other important constraint: Timing constraints. The latter is crucial in ISE flow because the tool needs to know at what speed the clock will be running. Delays in the FPGA may cause setup and hold violations to occur in a design, thus corrupting data. With the information about the clock given to the tool, it will compute the delay for each path on the FPGA and check if there is possibility of timing error.

This Lecture will be able add a Period Constraint, which is the major Timing Constraint to add in any synchronous design.

After all the required constraints are added, the design is ready for implementation.

In this Lecture, we will run a Post Route Simulation to demonstrate how it is done but this is an optional step as once implementation completed without error, the bitstream can be generated.

The same Simulator, ISIM, will be used and a simple test bench will be created only to kick off simulation.

Timing Analysis is about generating a report for the timing in a design. After implementation, timing analysis can be run and this will analyze each path in the design to check how much margin they have. If any path didn't not meet timing, it will be flagged in red and will be counted as a 'timing error'. The total amount of time by which the design is not meeting timing is called the 'timing score'.

After implementation passed successfully, the bitstream can be generated from a program called Bitgen and this is run from Project Navigator. The result is that a .bit file will be generated and deposited in the project directory. This is the file that will be used to configure the FPGA.

Using a program called iMPACT, which is integrated in ISE, the Basys 2 board can be accessed via a USB cable and the .bit file generated can be downloaded on the board.

This Lecture will show how this program is opened, the board is connected and design is loaded. The Home Alarm System will be tested on the board.

The Configuration will be done in two ways: (1) Loading the design directly on the FPGA and (2) the design is written in a PROM (Programmable Read Only Memory) found on the board. Method (1) allows the design to work as long as the board is powered but when it's powered off, the design will be lost as the FPGA has a volatile memory. Method (2) will allow the design to be loaded from the PROM each the power is turned back on.

This is the powerpoint of the course that you can download in pdf format. Please note that it is for your personal use only.