The advanced VHDL course includes advanced RTL features as well as verification behavioral capabilities :
- VHDL Configurations
- VHDL Arrays
- Modeling memories in VHDL, creating inferred memories in RTL
- Modeling and inferring FIFOs in VHDL
- VHDL Signal Hierarchy
- VHDL Generics , Records, and Alias
- VHDL File I/O , and TextIO
- Creating pseudo-code for simulations
- Developing VHDL Bus Functional Models
Understanding VHDL Configurations and how to use configurations in simulation.
VHDL Generics, Records and Multi-dimensional arrays for RTL and behavioral design and verification.
Using multi-dimensional arrays to model large memories, and how to infer RTL memories with arrays.
Discussion on designing asynchronous FIFOs with inferred RTL arrays.
How to utilize signal hierarchical access from a Test Bench.
Using VHDL File I/O to utilize input and output files during simulation.
Developing VHDL Pseudocode with File I/O to emulate software operations on your RTL code.
Utilizing the VHDL generate and alias statements in behavioral and RTL code.
Advance verification techniques available in the VHDL language.
Using Bus Functional Models to verify interfaces in your VHDL simulations.
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