System Design using Verilog from Udemy

What's inside

Learning objective

Verilog coding for digital circuits

Syllabus

Learners will learn various design technologies which are used to design a Integrated Circuit.

In this lecture learners will understand:

(1) Design Metrics

(2) System Design Technology

In this lecture we shall discuss:

(1) Fixed-Function IC Technology

(2) Advantages of Fixed-Function IC Technology

(3) Disadvantages of Fixed-Function IC Technology

In this lecture we shall discuss:

(1) Full Custom ASIC Technology

(2) Advantages of Full Custom ASIC Technology

(3) Disadvantages of Full Custom ASIC Technology

In this lecture we shall discuss:

(1) Semi-Custom ASIC Technology

(2) Advantages of Semi-Custom ASIC Technology

(3) Disadvantages of Semi-Custom ASIC Technology

HDL Role in System Design

In this lecture we shall discuss:

(1) PLA

(2) Example of PLA Implementation

In this lecture we shall discuss:

(1) PAL

(2) Example of PAL Implementation

In this lecture we shall discuss:

(1) FPGA

(2) Rooting Algorithm

In this lecture we shall discuss:

(1) Implementation of Logic in FPGA (Example-1)

(2) Implementation of Logic in FPGA (Example-2)

(3) Implementation of Logic in FPGA (Example-3)

Challenge Your Self - 1

Students will learn basics of Verilog data types, operators and Xilinx software to write and simulate a Verilog module

In this lecture we shall discuss:

(1) Hardware description language

(2) Structure of Verilog module

(3) Identifiers

(4) Comment

(5) White space

In this lecture we shall discuss:

(1) Program Structure in Verilog

(2) Level of abstraction

(A) Behavioural Level

(B) Dataflow level

(D) Switch Level

In this lecture we shall discuss:

Introduction to Xilinx Software

In this lecture we shall discuss:

Net Data Type

In this lecture we shall discuss:

(1) Register data type

(a) “reg” data type

(b) “integer” data type

(d) “time” data type

(2) Vectors

In this lecture we shall discuss:

Bitwise operators

In this lecture we shall discuss:

(1) Logical operators

(2) Reduction operators

In this lecture we shall discuss:

(1) Arithmetic Operator

(2) Relational Operator

(3) Equality Operator

(4) Shift Operator

In this lecture we shall discuss:

(1) Concatenate Operator

(2) Conditional Operator

(3) Replication Operator

Challenge Your Self – 2

In this section learners will understand the basics of Introduction to Behavioural, dataflow and Structure level of modeling

In this lecture we shall discuss:

(1) Structure Level (Gate Level)

(2) Predefined gates in Verilog Library

(3) Some Constraints

(4) Example-1: Write structure model of Half Adder

(5) Example-1 Half Adder Structure Model Software Demonstration

(6) Example-2: Write structure model of Full Adder

(7) Example-2 Full Adder Structure Model Software Demonstration

In this lecture we shall discuss:

(1) Behavioral Level Design

(2) Some Constraints

(3) Example-1: Write behavior model of Half Adder

(4) Example-2: Write behavior model of Full Adder

(5) Full Adder Behavior Model Software Demonstration

In this lecture we shall discuss:

(1) Dataflow Level Design

(2) Some Constraints

(3) Example-1: Write dataflow model of Half Adder

(4) Example-2: Write dataflow model of Full Adder

(5) Full Adder Dataflow Model Software Demonstration

In this section learners will understand how to write a testbench for simulating a Verilog module

In this lecture we shall discuss:

(1) Test bench

(2) Example-1 “and gate” (using Explicit Association)

(3) Example-2 “and gate” (using Positional Association)

In this lecture we shall discuss:

(1) Example-1 “and logic” Software Demonstration

(2) Example-2 Half Adder Software Demonstration

(3) Example-3 Half Adder Software Demonstration

In this lecture we shall discuss:

(1) Example-1 Verilog code of Full Adder and Test Bench

(2) Example-1 Full Adder Software Demonstration

In this section learners will understand how to write a structure level Verilog code use examples

In this lecture we shall discuss:

(1) Structure model of 2-to-1 Multiplexer

(2) Test bench of 2-to-1 Multiplexer

(3) Software Demonstration

In this lecture we shall discuss:

(1) Structure model of 2 to 4 Decoder

(2) Test bench of 2 to 4 Decoder

(3) Software demonstration

In this lecture we shall discuss:

(1) Block Diagram of 3-bit Full Adder

(2) Hierarchical Structure of 3-bit Full Adder

(3)Structure model of 3-bit Full Adder

(4) Instantiation

In this lecture we shall discuss:

(1) Test bench of Structure model of 3-bit Full Adder

(2) Software demonstration

In this section learners will understand how to write Behavioural level Verilog code using examples

In this lecture we shall discuss:

(1) Procedural Assignment

(2) The “initial” block

(3) Examples of the “initial” block

(4) Some short cuts in declarations

(5) The “always” block

(6) Example of the “always” block

In this lecture we shall discuss:

(1) “if” statement

(2) Behavior model of Level triggered D flip flop

(3) Software demonstration of Behavior model of Level triggered D flip flop

In this lecture we shall discuss:

(1) “if….else” statement

(2) Write behaviour model of 2 to 1 multiplexer

using “if….else” statement

(3) Test bench of 2 to 1 multiplexer

(4) Software Demonstration

In this lecture we shall discuss:

(1) “if….else” statement

(2) Write behaviour model of 4 to 1 multiplexer

using “if….else” statement

(3) Test bench of 4 to 1 multiplexer

(4) Software Demonstration

In this lecture we shall discuss:

(1) Write behaviour model of 2 to 4 Decoder

using “if….else” statement

(2) Test bench of 2 to 4 Decoder

(3) Software Demonstration

In this lecture we shall discuss:

(1) Write behaviour model of one bit comparator

using “if….else” statement

(2) Test bench of one bit comparator

(3) Write behaviour model of two bit comparator

using “if….else” statement

(4) Test bench of two bit comparator

In this lecture we shall discuss:

(1) Software Demonstration of one bit comparator

Software Demonstration of two bit comparator

In this lecture we shall discuss:

(1) “case” Statement

(2) Example-1: Behavior model of 2 to 1 multiplexer using “case” statement

(3) Test bench of 2 to 1 multiplexer

(4) Software Demonstration

In this lecture we shall discuss:

(1) Example-1: Behaviour model of 4 to 1 multiplexer using “case” statement

(2) Test bench of 4 to 1 multiplexer

(3) Software Demonstration

In this lecture we shall discuss:

(1) Write behavior model of 2 to 4 Decoder

using “case” statement

(2) Test bench of 2 to 4 Decoder

(3) Software Demonstration

In this lecture we shall discuss:

(1) Write behavior model of one bit comparator

using “case” statement

(2) Test bench of one bit comparator

(3) Software Demonstration

In this lecture we shall discuss:

(1) 7-Segment Display

(2) Verilog module of BCD to 7 Segment Decoder using “case” Statement

(3) Test bench of BCD to 7 Segment Decoder

(4) Software Demonstration

In this lecture we shall discuss:

(1) “while” loop

(2) “for” loop

(3) “repeat” loop

(4) “forever” loop

In this section learners will understand how to write a Behavioural level Verilog code for a sequential circuit

In this lecture we shall discuss:

(1) Verilog Code of Positive edge triggered D Flip Flop

(2) Verilog Code of Negative edge triggered D Flip Flop

(3) Software Demonstration

In this lecture we shall discuss:

(1) Verilog Code of Positive edge triggered JK Flip Flop

(2) Verilog Code of Negative edge triggered JK Flip Flop

(3) Test Bench

Software Demonstration

In this lecture we shall discuss:

(1) Verilog Code of Positive edge triggered T Flip Flop

(2) Verilog Code of Negative edge triggered T Flip Flop

(3) Test Bench

(4) Software Demonstration

In this lecture we shall discuss:

(1) Verilog Code of Positive edge triggered 3 Bit Up Counter

(2) Test Bench

(3) Verilog Code of Positive edge triggered 3 Bit Down Counter

(4) Test Bench

(5) Software Demonstration

In this lecture we shall discuss:

(1) Verilog Code (Behaviour Model) of 3 Bit Parallel In Parallel Out Register

(2) Test Bench

(3) Verilog Code (Structural Model) of 3 Bit Parallel In Parallel Out Register

(4) Test Bench

(5) Software Demonstration

In this lecture we shall discuss:

(1) Verilog Code (Behaviour Model) of Serial In Parallel Out Register

(2) Test Bench

(3) Software Demonstration

In this lecture we shall discuss:

(1) Verilog Code (Behaviour Model) of 3 Bit Serial In Serial Out Register

(2) Test Bench

(3) Verilog Code (Structural Model) of 3 Bit Serial In Serial Out Register

(4) Software Demonstration

In this section learners will understand the concepts using multiple always block

In this lecture we shall discuss:

(1) Multiple “always” block Example

(2) Test Bench

(3) Simulation Result

In this lecture we shall discuss:

(1) Verilog Code of Positive edge triggered D Flip Flop using Multiple “always” Block

(2) Test Bench

Simulation

In this lecture we shall discuss:

(1) Write behaviour model of 2 to 4 Decoder using multiple “always” statement

(2) Operation Explanation of 2 to 4 Decoder using multiple “always” statement

(3) Test bench of 2 to 4 Decoder

(4) Simulation

In this section learners will understand the concepts of Blocking and Non-blocking Statements

In this lecture we shall discuss:

(1) Procedural Assignment

(2) Blocking Assignment

(3) Examples of Blocking Statements

Simulation Results

In this lecture we shall discuss:

(1) Non-Blocking Assignment

(2) Examples of Non-Blocking Assignment

(3) Simulation result

In this section we shall discuss few examples of writing Verilog code

In this lecture we shall discuss:

(1) Dataflow Model of Full Subtrator

(2) Behavior Model of Full Subtrator using Expression

(3) Behavior Model of Full Subtrator using “if---else” Statements

(4) Structure Model of Full Subtrator

(5) Simulation

In this lecture we shall discuss:

(1) Truth Table of Binary to Gray Code converter

(2) Structure Model of Binary to Gray Code converter

(3) Behavior Model of Binary to Gray Code converter

(4) Dataflow Model of Binary to Gray Code converter

(5) Test Bench

(6) Simulation

In this lecture we shall discuss:

(1) Truth Table of 4 Bit Gray to Binary Code converter

(2) Structure Model of 4 Bit Gray to Binary Code converter

(3) Behavior Model of 4 Bit Gray to Binary Code converter

(4) Dataflow Model of 4 Bit Gray to Binary Code converter

(5) Test Bench

In this lecture we shall discuss:

(1) Write behaviour model of 1 to 2 Demultiplexer

(2) Write structure model of 1 to 2 Demultiplexer

(3) Test bench

(4) Software Demonstration

In this lecture we shall discuss:

(1) Block diagram and functional Table of 8 to 3 Priority Encoder

(2) Verilog Code (Behaviour Model) of a 8 to 3 Priority Encoder

(3) Verilog Code (Dataflow Model) of a 8 to 3 Priority Encoder

(4) Test Bench

(5) Software Demonstration

In this section learners will understand how to write a Verilog module using "cmos" switch

In this lecture we shall discuss:

(1) Switch Primitives in Verilog

(2) “nmos” Switch

(3) “pmos” Switch

(4) Example-1: CMOS Inverter

(5) Example-2: CMOS 2 input NAND Gate

(6) Example-2: CMOS 2 input NOR Gate

In this lecture we shall discuss:

(1) CMOS 3 input NAND Gate

(2) Software Demonstration

“cmos” Switch (Part III)

In this lecture we shall discuss:

(1) “cmos” Switch

(2)“cmos” 2 to 1 Multiplexer

Learners will learn how to write Verilog coded for defining Combinational and Sequential logics UDP

In this lecture we shall discuss:

(1) User Defined Primitives (UDP)

(2) Some Rules of UDP

(3) UDP of Two inputs AND gate

(4) UDP of Two inputs OR gate

In this lecture we shall discuss:

(1) UDP of Four inputs AND gate

(2) UDP of Four inputs OR gate

(3) UDP of full Adder

(4) UDP of multiplexer

In this lecture we shall discuss:

(1) UDP of Level Sensitive D Latch

(2) UDP of D flip-flop

In this lecture we shall discuss:

(1) UDP of T flip flop

(2) UDP of JK flip flop

Activities

Be better prepared before your course. Deepen your understanding during and after it. Supplement your coursework and achieve mastery of the topics covered in System Design using Verilog with these activities:

Review Digital Logic Fundamentals

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Solidify your understanding of digital logic concepts. This will provide a strong foundation for understanding Verilog implementations.

Browse courses on Boolean Algebra

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Review textbooks or online resources on digital logic.
Practice solving problems related to logic gate simplification and circuit design.
Familiarize yourself with different number systems (binary, hexadecimal) and conversions.

Read 'Verilog HDL' by Samir Palnitkar

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Enhance your Verilog skills with a dedicated language reference. This book provides in-depth explanations and examples.

View Verilog HDL A Guide to Digital Design and... on Amazon

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Read the chapters related to the specific Verilog constructs used in the course.
Experiment with the code examples provided in the book.
Use the book as a reference when writing your own Verilog code.

Read 'Digital Design and Computer Architecture' by Harris and Harris

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Gain a deeper understanding of digital design principles. This book will supplement the course material and provide a broader perspective.

View Digital Design and Computer Architecture on Amazon

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Read the chapters related to combinational and sequential logic design.
Work through the examples and exercises provided in the book.
Relate the concepts learned in the book to the Verilog code examples in the course.

Four other activities

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Implement Basic Logic Gates in Verilog

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Reinforce your understanding of Verilog syntax and basic gate implementations. This will improve your coding fluency.

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Write Verilog code for AND, OR, NOT, XOR, NAND, and NOR gates.
Simulate the gates using Xilinx software to verify their functionality.
Experiment with different input combinations and observe the output.

Create a Verilog Tutorial

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Deepen your understanding by teaching others. Creating a tutorial forces you to organize and explain concepts clearly.

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Choose a specific Verilog topic (e.g., always blocks, blocking vs. non-blocking assignments).
Write a clear and concise explanation of the topic.
Include code examples to illustrate the concepts.
Share your tutorial on a forum or blog.

Design a Simple ALU in Verilog

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Apply your Verilog knowledge to a practical design project. This will solidify your understanding of system design principles.

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Define the functionality of the ALU (addition, subtraction, AND, OR, etc.).
Write Verilog code for each functional unit of the ALU.
Integrate the functional units into a complete ALU design.
Create a testbench to verify the functionality of the ALU.

Contribute to an Open-Source Verilog Project

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Gain real-world experience by contributing to an open-source project. This will expose you to industry best practices and collaborative development.

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Find an open-source Verilog project on GitHub or GitLab.
Review the project's documentation and code.
Identify a bug or feature that you can contribute to.
Submit a pull request with your changes.

Career center

Learners who complete System Design using Verilog will develop knowledge and skills that may be useful to these careers:

IC Design Engineer

An IC Design Engineer designs integrated circuits. To be successful as an IC Design Engineer, you need to understand IC design technology, the IC design flow, and the role of hardware description languages like Verilog, all topics addressed in this course. Knowing full custom and semi-custom ASIC technologies, as can be covered in this course, also is very useful. The course covers the implementation of logic using MOS transistors, which is a key skill for an IC Design Engineer.

See salaries and explore the career path for IC Design Engineer

FPGA Engineer

An FPGA Engineer designs, develops, and tests digital circuits and systems using Field Programmable Gate Arrays. This course helps you learn the concepts of implementing logic in FPGAs. Through the course, you will also understand how to use Xilinx software for writing, simulating, and implementing Verilog code which you will need to master in this role. The discussion of FPGA rooting algorithms may be useful. Understanding the implementation of logic in FPGA, which the course covers, is critical for any FPGA Engineer.

See salaries and explore the career path for FPGA Engineer

Digital Design Engineer

A Digital Design Engineer designs and develops digital circuits and systems. Digital Design Engineers may find this course helpful because it explores the implementation of logic using various technologies including Fixed Function IC, Full Custom ASIC, and Semi-Custom ASIC. The material on Verilog coding is very relevant to the work that a Digital Design Engineer does. Knowing how to implement combinational and sequential logic using different modeling styles will also be useful for you as a Digital Design Engineer.

See salaries and explore the career path for Digital Design Engineer

VLSI Engineer

A Very Large Scale Integration Engineer focuses on designing and fabricating integrated circuits with a high density of components; this course may be useful as it covers the IC design flow and different IC design technologies. A VLSI Engineer will find the discussion of full custom and semi-custom ASIC technologies useful as well as MOS transistors. Furthermore, VLSI Engineers will benefit from the course's focus on Verilog, a hardware description language widely used in VLSI design and verification.

See salaries and explore the career path for VLSI Engineer

System on Chip Designer

A System on Chip Designer integrates various components into a single chip. Many System on Chip Designers use hardware description languages like Verilog to model and simulate their designs, so this course on system design using Verilog may be very useful. The course covers various IC design technologies and the role of HDL in system design. The course may also help because they can understand different modeling styles, which allows them to refine designs more rapidly.

See salaries and explore the career path for System on Chip Designer

Hardware Engineer

A Hardware Engineer designs, develops, and tests computer hardware components and systems. A strong command over Verilog is essential, and this course is centered on using Verilog for system design. The course also explores various IC design technologies, including Fixed Function IC, Full Custom ASIC, and Semi-Custom ASIC, all of which will expand the knowledge base of a Hardware Engineer. Furthermore, the course covers the IC design flow, giving you a more holistic view which is valuable for any Hardware Engineer.

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Embedded Systems Engineer

An Embedded Systems Engineer designs, develops, and tests embedded systems, which are computer systems with a dedicated function within a larger mechanical or electrical system. Embedded Systems Engineers often use hardware description languages like Verilog to design and implement digital circuits, making this course highly relevant. The coverage of PLDs and FPGAs may be useful for implementing logic in embedded systems. Through this course, an Embedded Systems Engineer can improve their understanding of Verilog coding.

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Hardware Verification Engineer

A Hardware Verification Engineer is responsible for verifying the correctness and reliability of hardware designs. The coverage of Verilog coding and simulation helps build a foundation for this role. Hardware Verification Engineers will want to know how to write test benches to simulate Verilog modules, and this course provides a way to understand this. Furthermore, the course covers implementation of combinational and sequential logic, so a Hardware Verification Engineer can master these topics.

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ASIC Verification Engineer

An ASIC Verification Engineer is responsible for verifying the functionality and performance of Application Specific Integrated Circuits. This course may be useful because it covers multiple levels of abstraction including behavioral, dataflow, and structural. The ASIC Verification Engineer must ensure that the ASIC design meets the required specifications and this course will help broaden your understanding. The course also covers writing test benches to simulate Verilog modules. This is crucial for an ASIC Verification Engineer.

See salaries and explore the career path for ASIC Verification Engineer

Electronics Engineer

An Electronics Engineer designs, develops, and tests electronic components, circuits, and systems. The focus on IC design technology helps you grasp the different methods for implementing logic. This course may be useful as it gives electronics engineers an overview of the IC design flow and introduces them to hardware description languages. By taking this course, an Electronics Engineer can master concepts such as combinational and sequential logic implementation.

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Test Engineer

A Test Engineer develops and implements testing strategies for electronic devices and systems. This course will increase your knowledge of how to use Xilinx software for writing and simulating Verilog code. Additionally, the course helps Test Engineers understand how to implement logic by using MOS transistors. Test Engineers will want to know how to write test benches to simulate Verilog modules, which will be helpful in debugging and testing the final product.

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Computer Architect

A Computer Architect designs the structure and behavior of computer systems, including CPUs, memory, and I/O subsystems; they should understand the implementation of logic in PLDs and FPGAs, as this course describes. The course's treatment of Verilog language constructs and operators helps you become more adept at modeling hardware behavior. As a Computer Architect, you are responsible for optimizing design metrics, a topic covered in this Verilog centered course.

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Product Engineer

A Product Engineer is involved in taking a product from design to manufacturing, and their duties include testing prototypes and resolving any issues that arise. This course on system design using Verilog may be useful because it will help you understand design metrics and system design technology. Product Engineers will want to understand the advantages and disadvantages of implementing logic using different IC technologies, which is covered in this course.

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Firmware Engineer

A Firmware Engineer develops the low-level software that controls hardware devices. This course may be useful if you want to understand the role of HDL in system design, which is what firmware is built upon. Firmware Engineers often work closely with hardware, thus understanding the advantages and disadvantages of implementation of logic using fixed function IC Technology, full custom ASIC technology, and semicustom ASIC technology may be helpful.

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Technical Consultant

A Technical Consultant provides expert advice and guidance to clients on technology-related issues; they should be equipped with a broader understanding of system design technologies. This course on system design using Verilog may be useful, as it enables you to understand the concepts of design metrics. A Technical Consultant can use the knowledge gained from this course to advise clients on the best approaches to system design and implementation, particularly in areas involving integrated circuits and digital logic.

See salaries and explore the career path for Technical Consultant

System Design using Verilog

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