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Verification Series Part 2

Hands-On SystemVerilog Projects

Kumar Khandagle

The VLSI industry can be divided into two branches, viz., design of RTL and verification of the RTL. Verilog and VHDL remain the popular choices for most design engineers working in RTL design. Functional verification could also be performed with the Hardware Description Language, but the Hardware Description Language has limited capabilities for performing code coverage analysis, corner case testing, and so on, and writing TB code may be impossible for complex systems at times.

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The VLSI industry can be divided into two branches, viz., design of RTL and verification of the RTL. Verilog and VHDL remain the popular choices for most design engineers working in RTL design. Functional verification could also be performed with the Hardware Description Language, but the Hardware Description Language has limited capabilities for performing code coverage analysis, corner case testing, and so on, and writing TB code may be impossible for complex systems at times.

SystemVerilog has become the primary choice of verification engineers to perform verification of complex RTL's. SystemVerilog object-oriented capabilities such as inheritance, polymorphism, and randomization allow users to find critical bugs with minimum effort.

Each complex system in FPGAs is built with the help of multiple subsystems. These subsystems can be either simple sequential components / simple combinational components / data communication protocols RTL / bus protocol RTL.

Once we understand strategies to perform verification of the common subsystems, you can easily perform verification of any complex system with the same logic.

Our objective for the course will be to build logic with the help of the fundamentals discussed in the first part of the course to perform verification of these common subsystems. We start our course by performing verification of data flipflops and FIFOs, then proceed to verification of common data communication protocols, viz. Finally, we will perform the verification of bus protocols, viz.

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What's inside

Learning objectives

  • Verification of memories viz. fifo
  • Verification of bus protocols viz. apb, ahb, axi, whishbone
  • Verification of interface communication protocols viz. spi, uart, i2c
  • Verification of simple compinational block viz. adder
  • Verification of simple sequential block viz. data flipflop

Syllabus

Verification Environment for D-FF
Course Pre-requisites
Summary
D-Flipflop P1
Read more
D-Flipflop P2
D-Flipflop P3
Design Code
UART P3
TB Codes
A11
A12
Verification environment for First In First Out (FIFO)
FIFO P1
FIFO P2
FIFO P3
TB code with comments
A21
Communication Protocol: Verification of Serial Peripheral Interface (SPI)
SPI Master P1
SPI Master P2
SPI Master P3
UART P4
TB Code
SPI with slave P1
SPI with slave P2
I2C Verification Environment P2
Verilog TB
Testbench Code
A31
Communication Protocol: Verification of UART
UART P1
UART P2
UART P5
APB read and Write Transactions P1
A41
Communication Protocol: Verification of I2C(Inter-Integrated Circuit)
Understanding start and stop conditions
I2C Write and Read Transactions
I2C Master FSM
I2C Master
I2C Slave
I2C Verification Environment P1
I2C Verification Environment P3
A51
Bus Protocol: Verification of APB_RAM
Understanding APB Signals
APB read and Write Transactions P2
Design
Testbench environment
TB environment
APB Old Videos Google Drive Link
Bus Protocol: Verification of AXI Memory
Understanding AXI Lite
Implementing Write
Implementing Read
Testing Write and Read
Building Verification environment P1
Building Verification environment P2
Building Verification environment P3
Building Verification environment P4
Verilog TB Code
SV TB Code
AXI Old Videos Google Drive Link
Bus Protocol: Verification of AHB Memory
Understanding AHB Signals P1
Understanding AHB Signals P2
Understanding Design P1
Understanding Design P2
Understanding Design P3
Understanding Design P4
Transaction Class
Generator Class
Driver Class P1
Driver Class P2
Driver Class P3
Monitor Class
Scoreboard Class
Verifying different Burst Modes P1
Verifying different Burst Modes P2
Bus Protocol: Verification of Whishbone Memory
Understanding Protocol
Understanding Design
Driver Class
Testbench Top

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Activities

Be better prepared before your course. Deepen your understanding during and after it. Supplement your coursework and achieve mastery of the topics covered in Verification Series Part 2: Hands-On SystemVerilog Projects with these activities:
Review Digital Logic Fundamentals
Strengthen your understanding of digital logic concepts. This will provide a solid foundation for understanding the SystemVerilog code and verification techniques used in the course.
Show steps
  • Review basic logic gates (AND, OR, NOT, XOR).
  • Study Boolean algebra and simplification techniques.
  • Practice designing simple combinational circuits.
Read 'Writing Testbenches using SystemVerilog' by Janick Bergeron
Enhance your understanding of testbench architecture and implementation. This book provides practical guidance on building robust and efficient verification environments.
View Writing Testbenches using SystemVerilog on Amazon
Show steps
  • Study the chapters on transaction-level modeling.
  • Review the examples of coverage-driven verification.
  • Practice implementing different testbench architectures.
Read 'SystemVerilog for Verification' by Chris Spear
Deepen your understanding of SystemVerilog verification methodologies. This book provides a comprehensive overview of the concepts and techniques used in the course.
View SystemVerilog for Verification: A Guide to... on Amazon
Show steps
  • Read the chapters related to constrained-random verification.
  • Study the examples of functional coverage implementation.
  • Practice writing SystemVerilog assertions.
Four other activities
Expand to see all activities and additional details
Show all seven activities
SystemVerilog Assertion Practice
Reinforce your understanding of SystemVerilog assertions. Regular practice will improve your ability to write effective assertions for verifying hardware designs.
Show steps
  • Write assertions for common design patterns (e.g., FIFOs, state machines).
  • Review assertion examples from the course materials.
  • Debug failing assertions to understand design errors.
Implement a Simple UART Verification Environment
Apply the concepts learned in the course by building a verification environment for a UART (Universal Asynchronous Receiver/Transmitter). This hands-on project will solidify your understanding of SystemVerilog and verification methodologies.
Show steps
  • Design a SystemVerilog testbench for a UART module.
  • Implement constrained-random stimulus generation.
  • Write assertions to check UART functionality.
  • Implement functional coverage to measure verification completeness.
Create a SystemVerilog Verification Cheat Sheet
Consolidate your knowledge of SystemVerilog verification by creating a cheat sheet. This will help you quickly recall important concepts and syntax.
Show steps
  • Summarize key SystemVerilog constructs (e.g., classes, interfaces, randomization).
  • Include examples of common verification techniques (e.g., constrained-random stimulus, functional coverage).
  • Organize the cheat sheet for easy reference.
Contribute to an Open-Source Verification Project
Gain real-world experience by contributing to an open-source verification project. This will allow you to apply your SystemVerilog skills in a collaborative environment and learn from experienced engineers.
Show steps
  • Find an open-source project related to hardware verification.
  • Identify a bug or feature to work on.
  • Contribute code, documentation, or test cases.
  • Participate in code reviews and discussions.

Career center

Learners who complete Verification Series Part 2: Hands-On SystemVerilog Projects will develop knowledge and skills that may be useful to these careers:
Verification Engineer
A Verification Engineer ensures the correctness and reliability of hardware designs. This course directly aligns with the core responsibilities of a Verification Engineer, focusing on practical SystemVerilog projects. Through hands-on exercises in verifying data flip flops, FIFOs, communication protocols like SPI, UART, and I2C, and bus protocols such as APB, AHB, and AXI, the course helps build a strong foundation in verification methodologies. The course's emphasis on SystemVerilog, the primary language for functional verification, makes it an ideal starting point. The course's practical approach to verifying common subsystems equips aspiring Verification Engineers with the skills needed to tackle complex system verification challenges. The course's coverage of various verification environments for different components helps to ensure that you are very well-prepared for this role.
See salaries and explore the career path for Verification Engineer
Design Verification Engineer
A Design Verification Engineer plays a critical role in ensuring the quality and reliability of hardware designs. This course directly helps in that it provides practical experience in SystemVerilog verification through hands-on projects. By verifying data flip flops, FIFOs, communication protocols like SPI, UART, and I2C, and bus protocols such as APB, AHB, and AXI, you can develop a strong understanding of common verification techniques. The course's coverage of SystemVerilog object-oriented capabilities is especially crucial, as it enables you to write efficient and effective testbenches for finding critical bugs. The course's learning objectives and syllabus help you enhance your skills in design verification.
See salaries and explore the career path for Design Verification Engineer
System on Chip Verification Engineer
A System on Chip Verification Engineer specializes in verifying the integration and functionality of complex SoCs. This course is highly relevant, as it focuses on the practical verification of common subsystems found within SoCs. The hands-on SystemVerilog projects, covering data flip flops, FIFOs, communication protocols like SPI, UART, and I2C, and bus protocols such as APB, AHB, and AXI, provide invaluable experience in verifying complex systems. The course's emphasis on SystemVerilog's object-oriented capabilities and the ability to find critical bugs with minimal effort can help you excel in SoC verification. The course's learning objectives and syllabus provide practical experience in ensuring the functionality of various SoC components.
See salaries and explore the career path for System on Chip Verification Engineer
ASIC Verification Engineer
An ASIC Verification Engineer is responsible for verifying the functionality and performance of Application Specific Integrated Circuits. This course directly aligns with the core skills required for this role, focusing on practical SystemVerilog projects. The course helps build a strong foundation in verification methodologies through hands-on exercises in verifying data flip flops, FIFOs, communication protocols like SPI, UART, and I2C, and bus protocols such as APB, AHB, and AXI. The course’s emphasis on SystemVerilog, which is a primary language for functional verification, makes it an ideal starting point. The knowledge gained from the course in verifying various components and employing SystemVerilog object-oriented capabilities can help you minimize effort in identifying critical bugs.
See salaries and explore the career path for ASIC Verification Engineer
Hardware Verification Lead
A Hardware Verification Lead oversees and guides a team of verification engineers. To excel as a Hardware Verification Lead, you must have in-depth knowledge of verification techniques and methodologies. This course's practical approach to SystemVerilog projects provides invaluable experience in verifying complex systems. The course's modules on verifying data flip flops, FIFOs, and communication protocols like SPI, UART, I2C, and bus protocols like APB, AHB, and AXI, offer you an understanding of common subsystem verification. This hands-on experience is crucial for leading a team effectively and making informed decisions about verification strategies. The course's detailed exploration of SystemVerilog's object-oriented capabilities and constrained-random verification can help you guide your team in finding critical bugs with minimal effort.
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Hardware Verification Consultant
A Hardware Verification Consultant advises companies on best practices for verifying hardware designs and can benefit from the practical knowledge gained in this course. The SystemVerilog projects, covering data flip flops, FIFOs, communication protocols like SPI, UART, and I2C, and bus protocols such as APB, AHB, and AXI, provide a diverse range of verification experiences. This helps you understand the challenges and solutions involved in verifying different types of hardware components which is critical for a consultant. The course’s learning objectives help you to offer valuable insights to clients looking to improve their verification processes. Having hands-on skills in SystemVerilog equips the consultant to provide tailored advice.
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FPGA Design Engineer
An FPGA Design Engineer develops and implements digital circuits on Field Programmable Gate Arrays. The course may be useful in that it covers the verification of common subsystems found in FPGAs. Verification of Data Flipflops, FIFOs, and communication protocols can help ensure that your designs function correctly and meet specifications. The course's practical SystemVerilog projects provide the ability to write testbenches and perform code coverage analysis, essential for FPGA design. The coverage of bus protocols such as APB, AHB, and AXI is beneficial as these are commonly used in FPGA-based systems for inter-component communication. The course’s learning objectives provide the ability to approach FPGA design with a focus upon verification.
See salaries and explore the career path for FPGA Design Engineer
Technical Trainer
A Technical Trainer teaches engineers how to use specific hardware or software tools and methodologies. This course's hands-on approach to SystemVerilog projects makes it valuable for a Technical Trainer specializing in hardware verification. By mastering the verification of data flip flops, FIFOs, communication protocols like SPI, UART, and I2C, and bus protocols such as APB, AHB, and AXI, you can effectively train others in these areas. The course can help one to develop clear and concise explanations of complex verification concepts and provide practical exercises that reinforce learning. The learning objectives of the course will allow you to be proficient in the space of hardware verification.
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RTL Designer
An RTL Designer creates Register Transfer Level descriptions of digital circuits using Hardware Description Languages. While this course focuses on verification, it may be useful in emphasizing the importance of designing RTL code that is easily verifiable. The course's hands-on projects in SystemVerilog can help you understand how to write testable RTL code. Furthermore, understanding the verification process for common subsystems like data flip flops, FIFOs, and communication protocols can help you design more robust and reliable RTL modules. The course’s content helps you become proficient in RTL design by understanding the importance of testability.
See salaries and explore the career path for RTL Designer
Verification Architect
A Verification Architect defines the overall verification strategy and methodology for complex hardware systems, and an advanced degree is typically required. This course may be useful in providing hands-on experience with SystemVerilog and various verification techniques. The practical projects, covering data flip flops, FIFOs, communication protocols like SPI, UART, and I2C, and bus protocols such as APB, AHB, and AXI, offer insights into the challenges of verifying different types of hardware components. The course’s learning objectives can help one to better understand the verification landscape and make informed decisions about verification strategies. The course's deep dive into diverse components helps build a foundation for this role.
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Hardware Engineer
A Hardware Engineer designs, develops, and tests computer hardware components and systems. This course may be useful in that it provides a strong foundation in hardware verification principles and techniques. By working through practical SystemVerilog projects, you can gain experience in verifying various hardware components, including data flip flops, FIFOs, and communication protocols like SPI, UART, and I2C. The course's coverage of bus protocols such as APB, AHB, and AXI can help you understand how different hardware components communicate with each other. The course's learning objectives and syllabus may also help you understand the importance of ensuring hardware functionality and reliability.
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Test Engineer
A Test Engineer develops and executes tests to ensure that hardware and software systems meet specified requirements. While this course focuses on verification using SystemVerilog, it can be useful in providing a deeper understanding of the verification process. By understanding the verification techniques used for data flip flops, FIFOs, communication protocols like SPI, UART, and I2C, and bus protocols such as APB, AHB, and AXI, you can develop more effective test plans and test cases. The course’s main learning objectives help you understand the importance of thorough testing and verification. The course's focus on verification helps prepare you for the test environment.
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Firmware Engineer
A Firmware Engineer develops low-level software that controls hardware devices. While this course focuses primarily on hardware verification, the skills learned can be valuable for a Firmware Engineer. Understanding how hardware components are verified helps you write more effective and robust firmware. The course's coverage of communication protocols like SPI, UART, and I2C is particularly relevant, as these protocols are commonly used in firmware development for communicating with peripheral devices. The skills that you will learn in this course may provide a more comprehensive understanding of the interaction between software and hardware.
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Application Engineer
An Application Engineer provides technical support to customers using complex hardware or software products. This course may be useful in that it provides a solid grounding in hardware verification principles and techniques. By working through practical SystemVerilog projects, you can better understand the challenges faced by customers who are verifying their hardware designs. The course's coverage of common subsystems like data flip flops, FIFOs, and communication protocols can help you troubleshoot customer issues and provide effective solutions. The course's learning objectives provide a strong foundation for a great Application Engineer.
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Electronic Design Automation Engineer
An Electronic Design Automation Engineer develops and supports software tools used for designing and verifying electronic systems. While this course focuses on using SystemVerilog for verification, it may be useful in understanding the needs of verification engineers and how EDA tools can better support their workflows. By working through the practical SystemVerilog projects, you can gain insights into the challenges faced by verification engineers and identify areas where EDA tools can be improved. The course’s main learning objectives underscore the importance of robust tools for efficient system verification. EDA engineers can use this perspective to build more effective tools.
See salaries and explore the career path for Electronic Design Automation Engineer

Reading list

We've selected two books that we think will supplement your learning. Use these to develop background knowledge, enrich your coursework, and gain a deeper understanding of the topics covered in Verification Series Part 2: Hands-On SystemVerilog Projects.
Cover image
SystemVerilog for Verification
Save
Comprehensive guide to SystemVerilog verification techniques. It covers constrained-random stimulus generation, functional coverage, and assertion-based verification. It is highly recommended as a reference text for this course, providing in-depth explanations and practical examples. This book is commonly used by verification engineers in the industry.
SystemVerilog for Verification: A Guide to Learning...
Paperback
$$
SystemVerilog for Verification: A Guide to Learning...
Kindle Edition
$$$
Cover image
Writing Testbenches using SystemVerilog
Save
Provides a practical guide to writing effective testbenches using SystemVerilog. It covers various verification techniques, including transaction-level modeling and coverage-driven verification. It valuable resource for understanding the practical aspects of SystemVerilog verification. This book is helpful in providing background knowledge and is commonly used as a textbook at academic institutions.
Writing Testbenches using SystemVerilog
Paperback
$$$

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Effort
8 total hours
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Instructor
Kumar Khandagle
Language
English
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