High-Level Synthesis for FPGA, Part 3

This course covers advanced topics in high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design. It quickly becomes a must-have skill for every hardware or software engineer keen on utilising FPGAs for their exceptional performance and low power consumption.

This course is the first to explain the advanced HLS design flow topics. It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises to practice and master the proposed methods and approaches.

This course is the third of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on multi-cycle design, advanced design, and optimisation techniques in HLS, the other courses in the series explain how to use single-cycle design techniques to develop combinational and sequential logic circuits in HLS.

What's inside

Learning objectives

Using multi-cycle design flow to develop sequential circuits in hls.
Implementing stream communication and computation in hls
Using fifo as the synchronisation mechanism between to connected module
Learning how to use an array variable inside an hls code
Connecting and and hls ip to brams in a vivado project
Working with pointers in hls
Working with axi protocol in hls
Loop pipelining optimisation in hls

Loop unrolling optimisation in hls
Loop flattening optimisation in hls
Loop rewinding optimisation in hls
Working with the hls-stream library in hls
Handshaking protocol and interfaces in hls
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Using multi-cycle design flow to develop sequential circuits in hls.
Implementing stream communication and computation in hls
Using fifo as the synchronisation mechanism between to connected module
Learning how to use an array variable inside an hls code
Connecting and and hls ip to brams in a vivado project
Working with pointers in hls
Working with axi protocol in hls
Loop pipelining optimisation in hls
Loop unrolling optimisation in hls
Loop flattening optimisation in hls
Loop rewinding optimisation in hls
Working with the hls-stream library in hls
Handshaking protocol and interfaces in hls
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Syllabus

By the end of this section, you will be familiar with this course's achievements and structure.

Introduction

Course Structure

By the end of this section, you will configure and set up all the hardware and software components required throughout this course.

How many block-level interfaces are available in Vitis-HLS?

Traffic lights

Read about what's good

what should give you pause

and possible dealbreakers

Focuses on using C/C++ for FPGA development, which allows software engineers to transition into hardware design without needing to learn VHDL or Verilog

Explores advanced HLS design flow topics, which are increasingly relevant as industry leaders adopt HLS for hardware and software platform design

Uses Xilinx HLS software and hardware platforms, which provides practical experience with industry-standard tools

Requires prior knowledge of single-cycle design techniques covered in earlier courses, which may necessitate additional learning for newcomers

Covers loop optimization techniques like pipelining, unrolling, and flattening, which are essential for achieving high performance in HLS designs

Explores AXI protocol and handshaking interfaces, which are crucial for integrating HLS IP with other components in a Vivado project

Reviews summary

Advanced hls design and optimization

According to learners, this course offers a deep dive into advanced High-Level Synthesis (HLS) techniques for FPGAs. Students particularly appreciate the coverage of topics like AXI protocol, pointers, and various loop optimization methods including pipelining and unrolling. Many find the course content highly relevant for professional work in hardware acceleration and design. While the course is generally seen as a valuable resource for mastering complex HLS concepts, some learners note that it assumes significant prior knowledge, especially from the previous parts of the series or general FPGA/HDL experience, making it potentially challenging for those without the recommended prerequisites.

Focuses on practical implementation and tool use.

"Using Xilinx Vitis HLS and Vivado throughout the examples helps solidify the concepts with actual tool flow."

"The examples connecting HLS IP to BRAMs in Vivado were particularly helpful for understanding integration."

"I appreciated the hands-on approach demonstrating streaming and memory mapped I/O implementations."

"Provides practical skills directly applicable to FPGA development projects."

In-depth exploration of key advanced HLS features.

"This course really digs into crucial advanced topics like AXI interfaces and pointer usage, which are essential for real-world designs."

"I gained a much better understanding of loop pipelining and unrolling optimizations after taking this module."

"The content on HLS-Stream library and handshaking protocols was very thorough and useful."

"Explains complex concepts like multi-cycle designs effectively."

Software installation and configuration can be tricky.

"Getting the Xilinx Vitis HLS and Vivado tools set up correctly was the most challenging part for me."

"Encountered issues with specific versions of the software and OS compatibility during installation."

"The initial setup section could be more detailed or provide better troubleshooting steps."

"Spend a good amount of time ensuring your toolchain is functional before diving into the content."

Requires strong background; not suitable for beginners.

"As part 3, it definitely requires a solid foundation from parts 1 and 2. Jumping in here without them would be difficult."

"You need a decent understanding of FPGAs, HDLs, and C/C++ before starting this course."

"Found the pace quite fast assuming prior knowledge. Might be tough if you aren't already somewhat familiar with HLS basics."

"This is strictly an advanced course; novices will likely struggle significantly."

Activities

Be better prepared before your course. Deepen your understanding during and after it. Supplement your coursework and achieve mastery of the topics covered in High-Level Synthesis for FPGA, Part 3 - Advanced with these activities:

Review AXI Protocol Fundamentals

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Reviewing AXI protocol fundamentals will help you better understand the AXI interfaces used in HLS and how they interact with hardware.

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Read documentation on AXI protocol specifications.
Watch introductory videos on AXI protocol.
Review examples of AXI transactions.

Read 'High-Level Synthesis: From Algorithm to Digital Circuit'

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Reading this book will provide a comprehensive understanding of the HLS design flow and optimization techniques, complementing the practical examples covered in the course.

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Read the chapters related to loop optimization and memory access.
Study the examples of HLS code and their corresponding hardware implementations.

Read 'FPGA Prototyping Using VHDL Examples'

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Reading this book will provide a deeper understanding of FPGA architecture and the hardware implementation of digital circuits, complementing the HLS concepts covered in the course.

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Read the chapters related to memory interfaces and data transfer.
Study the examples of VHDL code for common FPGA peripherals.

Four other activities

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Implement FIFO in HLS

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Practicing FIFO implementation in HLS will reinforce your understanding of stream communication and synchronization between modules.

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Write HLS code to implement a FIFO buffer.
Simulate the FIFO design to verify its functionality.
Synthesize the FIFO design and analyze its performance.

Document HLS Optimization Techniques

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Creating documentation on HLS optimization techniques will help solidify your understanding of loop pipelining, unrolling, and flattening.

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Research different HLS optimization techniques.
Write a report summarizing the techniques and their impact on performance.
Include examples of HLS code demonstrating the techniques.

HLS-based Image Processing Pipeline

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Starting a project to build an image processing pipeline using HLS will allow you to apply the concepts learned in the course to a real-world application.

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Design the image processing algorithms in C/C++.
Implement the algorithms in HLS.
Optimize the HLS code for performance and resource utilization.
Integrate the HLS IP into a Vivado project.
Test the image processing pipeline on an FPGA.

Contribute to an HLS Open Source Project

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Contributing to an open-source HLS project will provide practical experience in applying HLS concepts and collaborating with other developers.

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Find an open-source HLS project on platforms like GitHub.
Identify a bug or feature to work on.
Implement the fix or feature and submit a pull request.

Career center

Learners who complete High-Level Synthesis for FPGA, Part 3 - Advanced will develop knowledge and skills that may be useful to these careers:

FPGA Engineer

An FPGA engineer specializes in designing, implementing, and testing digital circuits using Field-Programmable Gate Arrays. This course is directly aligned with the work of an FPGA engineer, as it delves into advanced high-level synthesis techniques for FPGAs. The course teaches implementation of logic circuits on FPGAs using C/C++ without the need for traditional Hardware Description Languages. Any FPGA engineer will want to know how to use tools like Xilinx HLS software, covered in the course, and they will find great benefit in multi-cycle design, stream communication, loop optimization, and AXI interfaces. An FPGA engineer will be able to use these skills to improve the efficiency and performance of their designs.

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Digital Design Engineer

A digital design engineer designs and develops digital circuits and systems. This course is highly relevant to a digital design engineer because it focuses on advanced high-level synthesis techniques for implementing digital circuits on FPGAs. This allows a digital design engineer to develop their hardware using C/C++. The skills developed in this class, such as loop optimization, memory interfacing, and stream communication are important for any digital design engineer. An understanding of the topics in this course, gives a digital design engineer tools beyond traditional HDLs to explore.

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Hardware Engineer

The role of a hardware engineer involves designing, developing, and testing physical hardware components. This course on advanced high-level synthesis provides a unique approach to hardware design, focusing on C/C++ for FPGA implementation, which is highly relevant for a hardware engineer looking to stay at the cutting edge of technology. This is particularly useful to those seeking to leverage FPGAs for high-performance, low-power applications. The course's emphasis on multi-cycle design and optimization techniques will help a hardware engineer perform their duties effectively. A hardware engineer would also benefit from the skills acquired in the course's loop optimization, AXI protocol and HLS-Stream library material.

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Embedded Systems Engineer

An embedded systems engineer works on designing, developing, and testing software and hardware for embedded systems. This course offers valuable insight into how FPGAs can be efficiently programmed and used within embedded systems by using C/C++. An embedded systems engineer can improve their ability to develop and optimise embedded system hardware by understanding the material in this course. The course covers HLS design flow, including stream communication, loop optimization, and memory interfacing techniques, all of which are crucial for an embedded systems engineer to know when using FPGAs in their designs. These skills enable more effective and efficient development of embedded systems.

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Firmware Engineer

A firmware engineer develops low-level software that runs directly on hardware. This course provides skills in using high level synthesis to program FPGAs and move away from the traditional, more complex HDLs. The course's focus on topics including multi-cycle design, AXI protocol implementation and memory interfacing provide the skills that a firmware engineer needs to create efficient and powerful hardware interfaces. A firmware engineer that engages in this course will gain skills that allow them to develop innovative solutions for firmware development.

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Application Engineer

An application engineer provides technical support and develops solutions based on client needs. An application engineer can use this course to learn about high-level synthesis for FPGAs and how to best apply it to solve client challenges. The topics addressed in this course, from multi-cycle design to stream communication, can improve an application engineer’s approach when designing FPGA-based solutions. An application engineer that understands the use of HLS tools for hardware implementation can provide more relevant, timely and cost effective solutions to their clients.

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System Integration Engineer

A system integration engineer integrates various hardware and software components to create a functional system. A system integration engineer can use the high-level synthesis skills developed in this course to improve the integration of FPGA-based components into larger systems. The skills discussed in this course include stream communication and handshaking protocols which are crucial for system integration. A system integration engineer who is familiar with HLS will be able to create more efficient, and better communicating hardware systems.

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Technical Consultant

A technical consultant provides expert advice and solutions for technology related issues. This course provides the technical depth required to advise on the use of high level synthesis, and specifically in relation to FPGAs. Understanding the content of this course, including topics such as memory mapped I/O, HLS streaming, and loop optimisation, provides one with the practical experience to give excellent advice and consultations. A technical consultant who takes this course will be able to recommend specific solutions and technical implementations that are optimal.

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Verification Engineer

A verification engineer is responsible for ensuring that hardware and software designs meet their specifications. A verification engineer can leverage their understanding of the HLS design flow covered in this course to develop more effective testing and verification strategies for FPGA-based designs. This course covers multiple topics including working with pointers in HLS, AXI protocol usage, handshaking protocols, and loop optimization all of which can assist the work of a verification engineer. A verification engineer will better understand the hardware and how to test it by participating in this course.

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Computer Architect

A computer architect designs and develops the core structure of computer systems. This course is useful for a computer architect because it addresses the implementation of hardware using high-level synthesis. This course allows them to understand how hardware can be implemented with C/C++ on FPGAs. The material in the course, including loop optimization and stream communication, helps a computer architect improve the performance and efficiency of their hardware. A computer architect will find the discussion of design flows and optimizations relevant to their work.

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Software Engineer

A software engineer designs, develops, and tests software applications. While seemingly distant, this course on high-level synthesis provides a unique way for a software engineer to move into hardware design using their existing programming language skills with C/C++. Because a software engineer will most probably be familiar with C/C++, this course can help them develop an entry into hardware design. The course's focus on HLS techniques, including loop optimization and stream communication, will help a software engineer develop an understanding of how to apply their skills in hardware. The concepts this course covers provide a foundation for applying software design methodologies in a hardware setting.

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Research Scientist

A research scientist conducts research and experimentation in a specific field of science or technology. This course provides a hands on aproach to using HLS tools which may be of use to a research scientist that works on FPGA design or implementation. The techniques taught in this course, such as loop optimization, multi-cycle design, and stream communication can be used to to improve the performance of hardware algorithms. This course may help a research scientist advance their research into high-performance computing or embedded system design using FPGAs. A research scientist may find that the practical experience gained from this course would be valuable.

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Computer Systems Analyst

A computer systems analyst studies computer systems and their efficiency. A computer systems analyst can benefit from the high-level synthesis techniques presented in this course, especially when evaluating systems with FPGAs. Topics such as stream data flow and loop optimisations, that this course presents, allows a systems analyst to better understand hardware implementation tradeoffs. A computer systems analyst who takes this course will be better equipped to analyze and recommend solutions for system optimization.

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Algorithm Developer

An algorithm developer designs and develops algorithms for specific applications. The focus of this course on high-level synthesis for FPGAs can be used by an algorithm developer to enhance the efficiency of their algorithms by implementing them directly in hardware. This course teaches concepts such as loop optimization and pipelining, which are important for the development of high-performance algorithms using FPGAs. An algorithm developer can learn to develop algorithms that are optimized for hardware implementation by taking this course. They will learn how their work can be transferred from software to high speed hardware implementations more easily.

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System Architect

A system architect designs the overall structure and components of a complex system. The skills developed in this high-level synthesis course will help a system architect by providing a deep understanding of the trade-offs involved in hardware design. The techniques that this course teaches, including stream communication, multi-cycle design and HLS optimization techniques, will also be useful for a system architect when developing systems that include FPGAs. The system architect will understand the practical implications of hardware decisions by completing this course.

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High-Level Synthesis for FPGA, Part 3 - Advanced

What's inside

Learning objectives

Syllabus

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Advanced hls design and optimization

Activities

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