This Course will let you know about "How to Design FPGA based Signal Processing Projects on MATLAB/Simulink".
This Course will let you know about "How to Design FPGA based Signal Processing Projects on MATLAB/Simulink".
This course is on Designing FPGA based Signal Processing Projects with MATLAB/Simulink and FPGA Design Tool (Xilinx VIVADO/ISE), we are going to use Xilinx System Generator (interface between MATLAB/Simulink and VIVADO/ISE) and HDL Coder. From this two tools we can design our projects on traditional MATLAB/Sumilink design flow; using Blocks and integrating blocks in Simulink or using MATLAB codes and finally converting this two types of design in to HDL or into Bitstream so we can program FPGA from MATLAB/Simulink or VIVADO/ISE.
We have session on
MATLAB & Simulink are the best tools for Signal Processing Projects, while FPGA are best hardware platform for such type of Signal Processing Projects cause of it's flexibility and processing capabilities.
How to Download and Install MATLAB/Simulink and VIVADO or ISE. This lecture tells you about the version compatibility of MATLAB/Simulink and VIVADO or ISE.
This session introduces the Matlab/Simulink, System Generator, HDL Coder and HDL Verifier tools for FPGA Design. We also have some basic design flow and its features on this lecture.
This session much elaborate about the System Generator and different block available at System Generator for FPGA Design, System Generator based different design Flow.
Overview on System Generator, Basic project design methodology with system generator. We have lab session on this Section which are
-Lab 31: Basic System Generator Design for FFT
-Lab 32: Creating JTAG Configuration for FPGA Board in System Generator
This Lab is on basic FFT based design with System Generator. This lab session includes "How to include FFT block on System Generator, configure it, integrate other system generator blocks as gateways , wavescope on the design".
This Lab session is on How to create JTAG configuration for uploading/dumping Sys Gen based Design on Hardware Co-Simulation Method to FPGA. We have showed up the "Creating JTAG Configuration for the Previous Project targeting Spartan 3E FPGA ".
An overview of HDL Coder, IP core, HDL coder configuration with ISE as well as VIVADO has been introduced here. We also have details of LMS IP core design steps on Simulink.
This is the Lab session on HDL Coder, this lab session is on "Least Mean Square-LMS Filter Design with HDL Coder". The necessary resources (project sources) are already attached with this Video. You have to go through that sources and locate on Matlab/Simulink as workspace.
This lab is on Designing FIR Filter for Audio Processing with System Generator. You can take any audio from your local drive and process as shown in this lab session.
This Session is on Design, Simulation and Implementation of OFDM (Orthogonal Frequency Domain Multiplexing) on System Generator and Targeting Spartan 3E FPGA.
This session is on designing remaining receiver section from the previous lab and simulating the OFDM system on System Generator.
Implementing the Zedboard XADC and Pmod DA2 [DAC] on System generator for the interfacing project!
This lecture is overview session of "Vitis Model Composer(VMC)" which is available after 2021 or later version of Vitis/VIVADO. After 2020 version VIVADO comes inside Vitis Tool Suite. The previous extension of VIVADO with MATLAB+Simulink is System Generator while new version is called "Vitis Model Composer".
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