This course covers the VHDL Programming Language from the basic to the intermediate level. We have presented basics of VHDL Language, its syntax/semantics, conditional statements, process statement with example project on Quartus prime tool. We also have Lab session on Combinatorial circuit design, sequential circuit design and state machine design.
This course also have sessions on writing the testbench module and simulating it with Modelsim. Another method of simulation and verification of VHDL design, Vector Waveform Generator is also presented in this course with Example.
This course covers the VHDL Programming Language from the basic to the intermediate level. We have presented basics of VHDL Language, its syntax/semantics, conditional statements, process statement with example project on Quartus prime tool. We also have Lab session on Combinatorial circuit design, sequential circuit design and state machine design.
This course also have sessions on writing the testbench module and simulating it with Modelsim. Another method of simulation and verification of VHDL design, Vector Waveform Generator is also presented in this course with Example.
Another Important part of this course is "Structural Design Methodology" in VHDL, we showed the design of "Full Adder" using the "Half Adder" module with Structural Design Method.
This session is on "Overview of VHDL Programming Language, Intel Quartus Prime Tool and Basic Logic Gate Design in VHDL".
In this session we have presented the method design and simulation with Modelsim Simulator along with Intel Quartus Prime tool.
In this session we have presented the "vector waveform method" for simulation of VHDL design with Intel Quartus Tool.
This session is on different types of conditional statements in VHDL as with-select, when-else, if-else, case, etc. We also include session on how to use the "process statement" in VHDL.
We will design the Combinatorial Circuits as Adder, Decoder and Multiplexer in this session.
In this session, we are going to design the Full Adder using the Half Adder using the Structural Modeling Method!
In this session we will taught about the "flipflops", "registers" and "Counter" design in VHDL Language. We will do the LAB on "Counter design" in next session.
FSM design and implementation on "sequence detector" and "GCD Calculator" design in VHDL.
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