Complete Verilog HDL programming course with a perfect, well structured and concise course for freshers and experienced, as it is from fundamental level to the application level. This course discuss the concepts in Verilog HDL programming and properties compared with C-Language and discussing the features and advantages.
In this course we give information related to VLSI design flow for FPGA & ASIC and gives overview about both.
This course gives information on different styles of programming like Gate level, Data flow, Behavioral and switch level with examples.
Complete Verilog HDL programming course with a perfect, well structured and concise course for freshers and experienced, as it is from fundamental level to the application level. This course discuss the concepts in Verilog HDL programming and properties compared with C-Language and discussing the features and advantages.
In this course we give information related to VLSI design flow for FPGA & ASIC and gives overview about both.
This course gives information on different styles of programming like Gate level, Data flow, Behavioral and switch level with examples.
This course gives clear picture on verification, i.e. simulation and writing a test bench and some general examples like counter, clock diver using counter, pulse generator.
This courses explains how to write verification models using test benches with task and system tasks with Examples. These examples includes, file based system tasks such as writing data in to file, reading data from file and loading data in to memory and random data generator.
This courses shows clear picture on Finite State Machines (FSM)
how to draw,
how to realize it in to hardware model
how ro translate in to verilog code for both Mealy & Moore FSM with examples.
This course also shows some projects like Memory controller, FIFO controller and Error detection & correction using Hamming code, this improves ability to analyse and approach to Projects.
Finally it gives basic knowledge on FPGA's like core concept how bit file is loaded in to FPGA.
One can able to understand What HDL, need of HDL, what are different EDA tools available, difference between C & verilog, Properties of Verilog HDL, Difference between Simulation time and system time and How parallelism is achieved in Verilog HDL programming
One can able to understand 3 levels of design descriptions, gate level, Dataflow and Behavioral Models with an Example
Compiler Directives in Verilog
Block diagram for memory design & verilog program for write - read processes
switch level modeling of n-mos, p-mos gates and how to write programs for CMOS inverter and CMOS NOR gate
What is simulation, methods of simulation with example
Block diagram & Test bench environment for design counter
Block diagram & Test bench environment for design pulse generator
Functions & tasks and system tasks, basic system tasks with example showing display , monitor, stop, finish system tasks
File based system tasks and random generator system task, example of discussing all system tasks with test bench environment, printing data on console as well as output file
Read file data as input and write in to memory location using system task with example
brief overview on PLI concept and how to generate
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