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Are you a beginner or an enthusiastic hobbyist interested in digital circuits design using the Verilog Hardware Description Language? Did you try to learn Verilog HDL before, but found it very challenging? Are you curious if you have what it takes to become a digital chip designer or a functional verification engineer? Then you're in the right place.
Verilog Hardware Description Language easy as A,B,C
Are you a beginner or an enthusiastic hobbyist interested in digital circuits design using the Verilog Hardware Description Language? Did you try to learn Verilog HDL before, but found it very challenging? Are you curious if you have what it takes to become a digital chip designer or a functional verification engineer? Then you're in the right place.
Verilog Hardware Description Language easy as A,B,C
You'll learn the basics of digital circuits theory and we'll focus most of our energy on implementing practical coding examples with real digital circuits using Verilog. You will graduate this course with a strong foundation in Verilog HDL for both Digital Design and Functional Verification.
From the Digital Design perspective, you'll be able to:
start from a digital circuit diagram / schematic and implement synthesizable Verilog code for ASIC / FPGA
start from a functional description and implement synthesizable Verilog code for ASIC / FPGA
From the Functional Verification perspective, you'll be able to:
understand a functional description of a digital circuit and create stimuli for it
implement a self-checking testbench to validate the functionality of a digital circuit
You will easily differentiate between different Verilog coding styles (structural, dataflow, behavioral) and how to use them to design synthesizable digital circuits. You'll see just how easy modeling digital circuits using Verilog is.
At the end of the course you'll master Verilog industry-level coding techniques to get the best results for digital design or verification.
Learn how to use an industry-level Verilog HDL simulator
Simulations are a critical part in designing modern digital chips, thus you will install and learn how to use Modelsim - Intel FPGA Edition (free version for academic purpose). You will be able to create projects, simulate your Verilog code, and interpret the outputs using an world-class simulator.
Course Overview
This course is tailored for beginners who are interested in digital microelectronics, digital circuit design and verification. The course contains more than 158 bite-sized lectures out of which more than half are hands-on exercises labeled Action Time. Each Action Time has downloadable resources which you can simulate immediately using Modelsim. Most of these sections also contain challenges for you, so you'll write extra code that extends beyond the initial functionality.
Your first Verilog examples will be similar to a normal programming language (like C) to learn the operators, and, step-by-step, we'll advance together to the Hardware Description Language constructs, where Verilog procedures execute in parallel.
You'll learn how to use Verilog for combinational and sequential logic and how to combine the Structural / Dataflow / Behavioral coding styles to obtain digital circuits with a specific functionality. Your circuits will get more complex as you advance, some of them being composed of a hierarchy of sub-circuits.
Verilog combinational circuits you will implement during the course : logic gates, adders, comparator, binary encoder / decoder, priority encoder, multiplexers / de-multiplexers, seven segment display decoder, Arithmetical Logical Unit (ALU), etc...
Verilog sequential circuits you will implement during the course: flip-flops, latches, shift registers (..
Next, you'll experiment with Verilog functions and tasks and how to use them in testbenches and design.
In the final chapters you will design memories (SRAM and ROM), Finite State Machines, and more complex circuits like a FIFO and even a data encryption module.
A workflow with destination SUCCESS.
We start from real engineering problems and understand how a digital circuit solves that problem.
You are presented a real digital circuit, how it is used in the real world, then how to model and test it using Verilog.
You simulate it using Modelsim, and next I walk you through the results interpretation.
We do this process together every single time.... I explain the story behind the Verilog code so that, at the end of the course, you will be able to write the Verilog code behind the story.
Why learn Verilog HDL?
Chances are more than 50% that all the chips in the devices around you were designed with Verilog.
Working as a Digital Design or a Functional Verification engineer means to design today the technologies of tomorrow. This translates into having an exciting and challenging job with a great impact in the world. Since less than 2% of engineers choose this path and the semiconductor industry has never been busier, I'm pretty sure you will find yourself a good place in it.
Verilog is a good foundation for learning SystemVerilog, which is a very popular object-oriented design and verification language in the semiconductor industry.
Why did I create this course?
As an engineering student, I found it quite challenging to learn Verilog because it has a very steep learning curve and you need lots of know-how to be able to run even a simple example. Because of this, most students give up learning Verilog for a career in Digital Design or Verification and this also negatively impacts their academic results.
After 10+ years of industry experience, thousands of hours in Verilog, and academic research, I feel I've found the missing puzzle pieces that I didn't have back in the days. This course will show you the beauty and simplicity of digital circuits design using Verilog.
Ready? Set... GO.
Thank you for your interest in Verilog HDL for Digital Circuits Design and Functional Verification.
Ready to embark on your journey in mastering the basics of Verilog HDL for digital design and verification? Let's start this wonderful adventure.
Let's get to know each other!
A small and fast presentation of the course chapters.
Find out what Verilog HDL is and how you can use it!
Let's classify abstraction levels and how they are integrated in the Integrated Circuits Design Flow. Find out how Verilog can be a part of this flow!
The Modern Digital Design Flow is a generic flow used by the industry for making modern chips. Find out more!
Learn basic notions about Electronics Design Automation and the role of Simulation tools for the Verilog Hardware Description Language.
We will install a complete development environment from Intel FPGA. With it we will be able to simulate and synthesize our designs. All these tools are used only in Academic purposes.
Important Modelsim Installation Note
Download link: https://fpgasoftware.intel.com/
If you select Quartus Prime Lite Edition v21.1 (March 2021) you can see that it contains:
1. Quartus Prime (includes Nios II EDS)
2. Questa - Intel FPGA Edition(includes Starter Edition)
If you select Quartus Prime Lite Edition v20.1.1 (November 2020) you can see that it contains:
1. Quartus Prime (includes Nios II EDS)
2. ModelSim-Intel FPGA Edition (includes Starter Edition)
Modelsim and Questasim are products from Mentor that have the same menus, windows and appearance the sole difference being : "Questa Sim offers high-performance and advanced debugging capabilities, while ModelSim PE is the entry-level simulator for hobbyists and students. Questa Sim is used in large multi-million gate designs, and is supported on Microsoft Windows and Linux, in 32-bit and 64-bit architectures"
So you have 2 solutions and you may choose whatever you like:
1. Download version v21.1 and use Questa in the same way we use Modelsim (they will look the same for you)
2. Download version v20.1.1 and use Modelsim as the course suggests
Please contact me if you have issues installing the simulator and run the "Hello world" example. You can also contact me if you have any course related question and we'll definitely solve them.
All the best,
Ovidiu
This is your first simulation of Verilog code using a Modelsim project.
Congrats! Be proud that you've simulated your first piece of Verilog code!
Discover the 3 major groups of value objects used in digital design and verification with Verilog: Nets, Variables, and Parameters.
Write and simulate the Verilog code that calculates the sum and the product of two numbers.
Get familiar with the Verilog data types used to describe a hardware circuit.
Create a Verilog example where you perform logical operations between some variables using multiple procedures.
Learn how to represent data in a specific format using Verilog.
Play with several representation formats for data used in Verilog.
Learn how to handle multi-bit variables in Verilog.
A simple yet powerful example with vectors in Verilog.
As all programming languages Verilog has a set of powerful operators used to handle data, model behavior, and take decisions.
Verilog bit-wise operators are used to perform bit-by-bit logic operations between two inputs.
Perform several bit-wise operations between two vectors.
Verilog reduction operators are used to perform operations between the bits of the operand. The result is a 1ibt value.
A simple example where you exercise all the Verilog reduction operators.
Discover the simplicity behind Verilog logical operators.
A simple example where you will use Verilog logical operators.
In this example you will learn how and where to actually use Verilog logical operators. Using them wrong could lead to undesired behavior that is hard to debug.
Verilog also has all the simple mathematical operators that everybody knows. Check them out!
A simple exercise with all the Verilog arithmetic operators.
Shifting operations are the very core of data handling. Let's discover the logic shift and the arithmetic shift Verilog operators.
Let's shift some data using all the Verilog shift operators.
Verilog relational operators are used to compare data. The result of a comparison is 1bit and it can have the value 0 / 1 / X.
Let's compare some data using the Verilog relational operators!
Discover the case equality and logical equality Verilog operators.
Let's compare some data using the Verilog equality operators!
Discover the conditional operator. This operator takes 3 operand that's why it is also called a ternary operator.
Let's do a simple example for the conditional operator!
The concatenation operator is used to join bits from different sources for creating new buses.
In this easy example you'll learn how to use the Verilog concatenation operator.
The Verilog replication operator is used to make data patterns.
This easy example will show you how to use the Verilog replication operator.
Operators precedence is a mechanism that says what operators get to execute first in an expression. It is extremely important to know this concept as complex expressions may hide faulty behavior if the precedence is not respected.
In this simple example you'll get familiar with Verilog operators precedence and explore some corner cases.
Answer some simple Verilog Operators questions to check out your newly acquired skills!
The Verilog module is basic building block for any design. Any chip designed in Verilog is a collection of modules exchanging data.
It's time to do your first testbench and instantiate you first Design Under Test. We're moving up in the world...
A small introduction in testbench architectures. We'll use this on all the examples in this course.
Each Verilog module is simulated in a time frame. Data flows from the module's inputs to the outputs and gets plotted by the simulator in a waveform.
Generate a simple waveform and get familiar with time units and signals with four states values (1/0/X/Z).
As life taught us, almost all problems have multiple solutions. In Verilog you can describe the same behavior by using a variety of coding styles.
Discover what Structural Design is and how it can be used in Verilog.
Implement a simple circuit that calculates the sum of two bits. You also get to implement the testbench for it.
Discover what Dataflow Style is and how it can be used in Verilog.
Discover what Behavioral Style is and how it can be used in Verilog.
Implement multiple Verilog procedures and see how they are executed in parallel.
Let's design an 1bit FULL ADDER using all 3 Verilog coding styles.
Implement a simple circuit that calculates the sum of two bits and a carry using the Structural style. You also get to implement the testbench for it.
Implement a simple circuit that calculates the sum of two bits and a carry using the Dataflow style. You also get to implement the testbench for it.
Implement a simple circuit that calculates the sum of two bits and a carry using the Behavioral style. You also get to implement the testbench for it.
Let's design a 4bit FULL ADDER using all 3 coding styles!
Implement a simple circuit that calculates the sum of two 4bit inputs and a carry using the Structural style. You also get to implement the testbench for it.
Implement a simple circuit that calculates the sum of two 4bit inputs and a carry using the Dataflow style. You also get to implement the testbench for it.
Implement a simple circuit that calculates the sum of two 4bit inputs and a carry using the Behavioral style. You also get to implement the testbench for it.
Discover Verilog Structural design.
What are Verilog built-in primitives and how to use them.
Play with all Verilog built-in primitives.
This simple circuit is present in ALL modern chips that exist on land, air and sea. Find out more!
Implement an 1bit multiplexer and a testbench for it, using Verilog.
It does the opposite as a multiplexer does. Find out more!
Save
Instructor helps with issues
Covers key Verilog and digital concepts
Learning with Modelsim/Questa tools
Concepts explained step-by-step
Emphasis on coding and simulation practice
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