VSD - Clock Tree Synthesis - Part 1

Kunal Ghosh

Clock Tree Networks are Pillars and Columns of a Chip.

With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.

The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.

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What's inside

Learning objectives

Cts quality checks (skew, power, latency, etc.)
H-tree
Quality check of h-tree
Clock tree buffering
Buffered h-tree

H-tree with uneven spread of flops
Advanced h-tree for million flops
Power aware cts (clock gating)
Static timing analysis with clock tree

Cts quality checks (skew, power, latency, etc.)
H-tree
Quality check of h-tree
Clock tree buffering
Buffered h-tree
H-tree with uneven spread of flops
Advanced h-tree for million flops
Power aware cts (clock gating)
Static timing analysis with clock tree

Syllabus

INTRODUCTION

Introduction to Clock Tree Synthesis

Clock Tree Quality Check Parameters

Skew and Pulse Width Check

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Activities

Be better prepared before your course. Deepen your understanding during and after it. Supplement your coursework and achieve mastery of the topics covered in VSD - Clock Tree Synthesis - Part 1 with these activities:

Review Digital Integrated Circuits

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Review key ideas in digital integrated circuits to strengthen your foundation for this course.

View Digital Integrated Circuits: A Design... on Amazon

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Read through the first four chapters of the book.
Summarize the key concepts of each chapter in your own words.

Solve practice problems on clock tree quality checks

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Strengthen your understanding of clock tree quality checks by solving practice problems.

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Find a set of practice problems on clock tree quality checks.
Solve the problems and review your answers.

Build a simple clock tree for a small circuit

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Practice the concepts of clock tree design by creating a basic implementation in Verilog.

Browse courses on Verilog

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Design a small digital circuit with multiple registers.
Write a Verilog module to implement the clock tree for your circuit.
Simulate your design to verify its functionality.

Two other activities

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Create a presentation on clock tree synthesis techniques

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Develop a deeper understanding of clock tree synthesis by exploring different techniques and presenting your findings.

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Research various clock tree synthesis techniques.
Create a presentation that explains the advantages and disadvantages of each technique.
Present your findings to a group of peers or mentors.

Develop a clock tree optimization tool

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Apply your knowledge of clock tree design to create a tool that can optimize clock trees for specific metrics.

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